JPS62224849A - Data processing system - Google Patents

Abstract

PURPOSE:To upgrade the rate of data transfer by providing the second address/ data bus connecting only between an incorporated memory and a direct memory access DMA controller in addition to a main bus, and enabling the supply of consecutive source addresses. CONSTITUTION:In a single-chip microcomputer, a data transfer (DMAC) control circuit 18 to execute the direct transfer of data between an external peripheral equipment (external memory) 20 and the incorporated memory 12, is provided. Between the circuit 18 and the memory 12, the second address bus 17a and the data bus 17b are provided. Consequently, a destination address can be outputted in parallel with a read data immediately after the data starts to get on the data bus 7b i.e. before a source address disappears. Furthermore, at the time when the latch of the read data by the circuit 18 ends and the source address comes to be unnecessary, the next source address can immediately be outputted to read out the next transfer data. As a result, data of plural consecutive bytes can be transferred with a high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data processing technology and a technology that is particularly effective when applied to a data transfer method in a microcomputer system. (referred to as microcontrollers).

[Prior Art] In microcomputer systems, it is often necessary to perform large-scale data transfer between data input/output devices such as CRT terminals, hard disks, or floppy disks, and memory or between memories. In that case, if the microprocessor performs such data transfer (block transfer) using software, the burden on the microprocessor increases and the system throughput decreases.

Therefore, DMA is used as a device to control data transfer between such devices instead of a microcomputer.
(direct memory access) controller is provided.

[Problems to be Solved by the Invention] However, even if such an MA controller is used, it is not possible to transfer blocks of data between the internal memory of a single-chip microcomputer and an external memory or disk device. Ta.

In other words, conventional single-chip microcontrollers.

For example, as shown in Figure 3, a microprocessor (hereinafter referred to as CP) controls internal execution units according to a program.
(referred to as U) 1, a ROM (read-only memory) 2 that stores operating programs of this CPU, etc., and a RAM (random memory) that mainly provides a work area for the CPU 1.
It consists of an access memory (access memory) 3, a serial communication interface circuit 4, a timer circuit 5, and input/output ports 8 to 6d, etc., and these circuits are connected to each other via an internal address bus 7a and an internal data bus 7b. There is.

An address bus 7a and a data bus 7b can be connected to the boat 6c via a multiplexer 8. Furthermore, a mode switching circuit 9 is provided which determines the operation mode after the microcontroller is reset by setting appropriate external terminals to predetermined states. functions as a data input/output function or an address output function, and also functions as a data input/output function or an address output function, and
is made to function as a data input/output function or a function of multiplexing a data bus and an address bus.

As a result, the single-chip microcomputer shown in FIG. 3 has an expandable address space and can also access external memory.

Regarding such single-chip microcontrollers.

[Described in the data book "Hitachi Microcomputer, 8-bit 16-bit Microcomputer" published by Hitachi, Ltd. in September 1982, pages 243 to 253.

Therefore, in such a single-chip microcontroller, for example, data is read from an external memory and internal R
When writing to AM3, or vice versa, as shown in FIG. 6d etc. Then, it is necessary to output a destination address (transfer destination address) and transfer the first read data Dr held in the input/output port d to the internal data bus 7b or an external bus as write data Dw.

Therefore, it takes two cycles (bus cycle) for reading and writing to transfer one byte of data, and especially in block transfer, the data transfer speed becomes slow and
This has the disadvantage that the load on the CPU increases and the throughput of the entire system decreases.

An object of the present invention is to improve the data transfer speed in a data processing system such as a microcomputer system.

Another object of the present invention is to reduce the load on the CPU during data transfer in a microcomputer system, thereby improving the throughput of the entire system.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for Solving the Problems] Representative inventions disclosed in this application will be summarized as follows.

In other words, a DMA controller is built into the single-chip microcontroller, and in addition to an internal address bus and a data bus that can be connected to an external bus via input/output ports, there is also a second address bus that connects only between the DMA controller and the built-in memory. By providing the /data bus, addresses can be output to the built-in memory in parallel with outputting addresses to the outside.

[Operation] According to the above-mentioned means, it is possible to supply continuous source addresses, improve the data transfer rate, and
This achieves the above objective of reducing the load on the CPU and improving the throughput of the entire system.

[Embodiment] FIG. 1 shows an embodiment in which the present invention is applied to a single-chip microcomputer.

Although not particularly limited, each circuit block surrounded by a chain line A in the figure is formed on one semiconductor chip such as a single crystal silicon substrate.

In this embodiment, microprocessor 1 and program R
Built-in memory 12 such as OM and working RAM and peripheral circuits 14 such as interface circuits and timer circuits
are organically coupled to each other by an internal address bus 7a and an internal data bus 7b, similar to the conventional system shown in FIG. Internal address bus 7a and internal data bus 7b are connected to external address bus 27a and external data bus 27b via input/output ports. As a result, when the single-chip microcomputer A is set to the external expansion mode, the external address bus 27
It is possible to access external memory and external peripherals 20, such as Ilo, connected to the chip via data bus 27b and data bus 27b.

Furthermore, in this embodiment, a data transfer control circuit (DMAC:) 18 is provided in the single-chip microcomputer A for directly transferring data between the external peripheral device 20 and the built-in memory 12. . Moreover, there is a second
An address bus 17a and a data bus 17b are provided.

Address buses 7a and 17a are data transfer control circuit 1
The control signal 9a generated by the multiplexer 8a
and is connected to the built-in memory 12 via an address bus 37a for the built-in memory. Similarly, data buses 7a and 17a are controlled by control signal 9a.
It is multiplexed by multiplexer 8b and connected to built-in memory 12 via data bus 37b for built-in memory. Note that the data transfer control circuit 18 is as follows.

DMA in conventional microcomputer systems
Like the controller, it is also connected to the main address bus 7a and data bus 7b.

The data transfer control circuit 18 of this embodiment has two internal address calculation units or address counters, and outputs different address signals to the address buses 7a and 17a at the same time, so that the built-in memory 12 and the external The peripheral devices 2o can be accessed simultaneously.

Therefore, when performing normal data processing, the single-chip microcomputer of this embodiment uses only one microprocessor.
are address buses 7a, 37a and data buses 7b, 37b.
can be used to read program instructions and necessary data from the built-in memory 12, and to store data obtained through processing in the built-in memory 12.

Therefore, when it becomes necessary to transfer a large amount of data such as block transfer between the external memory 20 and the built-in memory 12, the microprocessor 1 transfers data to the data transfer control circuit 1.
A direct transfer command is given to 8. Then,
As shown in FIG. 2, the data transfer control circuit 18 first outputs the source address SAI to the address bus 7a. As a result, the read data Drl read from the external memory (2o) is latched into the data transfer control circuit 18 through the internal data bus 7b from the input/output capotro. At the same time, the data transfer control circuit 18 outputs the destination address DAI onto the second address bus 17a. At the same time, the control signal 9a causes the multiplexer 8a to
The selected address bus is switched from 7a to 17a, and the destination address DAI is also output to the address bus 37a. Further, following this, the internally latched data is output onto the second data bus 17b as write data Dwl. At the same time, the control signal 9b switches the data bus selected by the multiplexer 8b from 7b to 17b, and the write data DWI is also output to the data bus 37b.

As a result, data read from the external memory (20) is written to a predetermined address in the built-in memory 12. Moreover, the data transfer control circuit 18 uses the address bus 1
7a, 37a and data buses 17b, 37b, destination address DAI and write data Dw
While outputting 1, the main address bus 7a
The next source address SA2 is outputted in parallel.

The above data transfer is from the external memory (20) to the built-in memory 12. However, when data is transferred from the built-in memory 12 to the external memory (20), the source address SAi is transferred to the address bus at the same timing as above. 17a, 3
7a, and the destination address DAi and write data Dwi are output to the main address bus 7a, data, and 7b.

In the conventional transfer method in a single-chip microcomputer shown in FIG. 4, a source address is output, read data is read, and then a destination address is output. On the other hand, if the transfer method of the above embodiment is followed,
The destination address DA can be output in parallel immediately after the read data starts to be loaded on the bus, that is, before the source address SA runs out. Furthermore, when the read data has been latched and the source address is no longer needed, the next source address can be output immediately and the next transfer data can be read.

This makes it possible to transfer multiple consecutive bytes of data (block transfer) at twice the speed compared to the conventional technology.

The data transfer control circuit 18 includes address bus output registers 100a and 101a, as shown in FIG.

It has data bus input/output registers 100b and 101b.

100a and 100b are connected to an address bus 7a and a data bus 7b, respectively, and the bus 7a.

The contents are updated in accordance with the timing of 7b.

101a and 101b are address buses 17a and 101b, respectively.
The bus 17a is connected to the data bus 17b.

The contents are updated in accordance with the timing of 17b.

100b and 101b are connected inside the data transfer control circuit 18. In addition, the control register 102
multiplexer control signal 9a.

9b is controlled.

In the above embodiment, the case where it is applied to a single-chip microcomputer has been described, but the present invention is a multi-chip device in which the microprocessor 1, memory 12, and data transfer control circuit 18 are each formed on separate chips. It can also be applied when configuring a microcomputer system.

However, according to the present invention, the data transfer control circuit (DMA
Since two buses are connected to the controller (controller), when configuring a multi-chip system, the buses may become quite complex and the system may become large. On the other hand, with a single-chip microcomputer, a bus is formed on the chip, so the chip size is somewhat larger, but the system can be constructed relatively easily compared to a multi-chip case.

[Effect] In addition to the main address bus and data bus, a second address/data bus is provided that connects only the DMA controller and the built-in memory, so the source address and destination address can be output in parallel. By the action of being able to.

This makes it possible to supply continuous source addresses, improves data transfer speed, reduces the load on the CPU, and improves the throughput of the entire system.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor.

[Field of Application] In the above description, the invention made by the present inventor was mainly applied to a single-chip microcomputer, which is the field of application that formed the background of the invention, but the invention is not limited thereto.

For example, IC memory and other microcomputer peripherals
It can be used when a DMA controller is built into the SI.

[Brief explanation of drawings]

FIG. 1 is a block configuration diagram showing an example of applying the present invention to a single-chip microcomputer, FIG. 2 is a timing chart showing an example of the timing of direct data transfer in the single-chip microcomputer, and FIG. is a block diagram showing an example of a conventional single-chip microcomputer; Figure 4 is a timing chart for continuous data transfer in a conventional single-chip microcomputer; Figure 5 is a diagram of a data transfer control circuit. This is a concrete block diagram. ], ... microprocessor, 2 ... lead
Only memory, 3...Random access memory, 6...I/O port, 7a...Main address bus, 7b...Main data bus, 12...
・Built-in memory 1c 14--Peripheral circuit, 17a...Second address bus, 17b...Second data bus, 18
...Data transfer control circuit, 2o...External peripheral device (external memory), 27a...External address bus,
27b...External data bus, 37a''゛°°Address bus for built-in memory, 37b...Data bus for built-in memory, 8a...Address bus multiplexer, 8b...Data bus multiplexer, 9
a...Address bus multiplexer control signal, 9b
...Data bus multiplexer control signal. ＼ −、′ Fig. 3

Claims (1)

[Scope of Claims] 1. A data processing system consisting of a microprocessor, memory, and peripheral devices, wherein the main address bus and data bus connecting the microprocessor, memory, and peripheral devices are connected through the microprocessor. A data transfer control circuit is connected to directly transfer data between the memory and the peripheral device without
A data processing system characterized in that the data transfer control circuit and the memory are connected by a second address bus and a data bus. 2. Part of the data transfer control circuit, memory, and peripheral devices are configured together with the microprocessor on one semiconductor chip, and the second address bus and data bus are also formed on the chip. A data processing system according to claim 2.