JPH05189362A - Bus conversion system - Google Patents

Abstract

PURPOSE:To provide a bus conversion system which cuts the quantity of materials by simplifying a bus converting circuit and shortens time for common memory access at the time of the continuous access of a common memory. CONSTITUTION:In the input/output package of a common memory system having a high-order CPU bus which is different from an EISA bus or an ISA bus, a means 4 is provided so as to convert an input/output instruction to the input/ output package from high-order CPU 1 having the EISA bus or the ISA bus into common memory access in the input/output package. Then, the input/output package is connected with the EISA bus of the ISA bus by way of the conversion means.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus conversion system for converting between different buses, for example, EISA.
(Extended Industry Standard Architecture) Bus
Or ISA (Industry Standard Architecture)
The present invention relates to a bus conversion system suitable for connecting an input / output package having an upper CPU bus different from the bus to an EISA bus or an ISA bus, and for accessing a shared memory of the input / output package.

[0002]

2. Description of the Related Art Conventionally, as this type of technology, for example,
The technique disclosed in JP-A-60-20258 is known. This technique has a conversion device for converting an input / output command from a higher-level device into an input / output command suitable for a system connected to a lower level. The conversion device described above converts an input / output instruction from the processor into an input / output instruction that matches the input / output processing device, and instructs the input / output processing device to execute this.
The input / output processing device is activated by this execution instruction, controls the input / output operation according to the converted input / output instruction, and reports the status report word as the execution result of this input / output operation to the conversion device. The conversion device converts the above status report word into a format that can be processed by the processor, and reports the converted status report word to the processor.

[0003]

The above-mentioned conventional technique is provided with a plurality of conversion circuits for converting an input / output instruction from the upper device side into an input / output instruction matching the lower side device according to the type of the input / output instruction. As a result, since the upper side accesses the lower side, there is a problem that the quantity of the conversion circuit increases. Further, when the lower memory is continuously accessed, conversion processing of an input / output instruction is required for each access, which causes a problem of low processing speed. The present invention has been made in view of the above circumstances, and an object thereof is to provide a bus (A) different from the above in a shared memory type input / output package having a certain upper CPU bus (B).
A bus that simplifies the bus conversion circuit connected to the bus and reduces the amount of physical quantity, and does not require address value specification from the host CPU during continuous access to the shared memory, thus shortening the time required for shared memory access. To provide a conversion system.

[0004]

The above objects of the present invention are as follows:
A shared memory type I / O package having a certain upper CPU bus (B) shares an I / O command for the I / O package from the upper CPU having a different bus (A) from the above in the I / O package. This is achieved by a bus conversion system characterized in that means for converting to memory access is provided and the input / output package is connected to the bus (A) through the conversion means.

[0005]

In the bus conversion circuit according to the present invention, a communication control adapter having a certain upper CPU bus (B) is directly connected to a bus (A) different from the above to access the shared memory of the communication control adapter. Since it is possible to perform the above, it is possible to obtain the following respective effects in the above example. (1) Utilizing the circuit of a communication control adapter having a higher-level CPU bus different from the already developed EISA bus or ISA bus, it is possible to easily and newly develop a communication control adapter having an EISA bus or ISA bus in a short period of time. What you can do. (2) The development cost can be reduced. (3) It is possible to suppress the increase in the amount of hardware at the time of the above development to a low level, and realize the downsizing of the communication control adapter and the reduction of manufacturing cost.

[0006]

Embodiments of the present invention will now be described in detail with reference to the drawings. In the examples shown below, EISA /
Take the ISA bus and non-EISA / ISA bus as examples. FIG. 1 is a diagram showing a configuration of a system including a communication control adapter which is an embodiment of the present invention. The communication control adapter 3 shown in this embodiment includes a lower non-EISA / ISA bus 5, a local CPU 6, a local CPU bus 7, a ROM 8, a shared memory controller 9, a shared memory bus 10, and a shared memory 1.
1, the communication control unit 12 and the bus conversion circuit 4, and is connected to the upper CPU 1 by the upper EISA / ISA bus 2. FIG. 2 shows a detailed configuration of the bus conversion circuit 4 described above. The bus conversion circuit 4 according to the present embodiment includes an upper data bus control unit 16, an I / O address decoding unit 17, a shared memory address register 20,
It comprises a shared memory data register 21, a lower data bus control unit 22, a lower address bus control unit 23, and a timing control unit 24. I / O address decoding unit 1
When accessing the shared memory address register 20 and the shared memory data register 21, the reference numeral 7 decodes the I / O addresses assigned to the shared memory address register 20 and the shared memory data register 21 from the upper address bus 14, Any one of the memory data register select signals 19 is output.

The shared memory address register 20 is a register for setting the address of the lower shared memory 11, and the shared memory data register 21 sets the data to be written in the lower shared memory 11, or the lower memory. This is a register that stores read data from the shared memory 11 of FIG. The timing control section 24 counts up the set value of the shared memory address register 20 from the upper side input / output instruction control signal 15 and the shared memory data register select signal 19 by the shared memory address register count up signal 25 and the shared memory data register 2
Shared memory data register latch signal 26 which is a latch signal of 1; lower side data bus control section control signal 27 for controlling lower side data bus control section 22 for controlling data input / output of lower side data bus 31; lower side address bus Lower address bus control unit 2 for controlling address output to 32
Lower side address bus control unit control signal 28 for controlling
It outputs the respective signals of the upper data bus control unit control signal 30 and the lower memory access control signal 29 which control the upper data bus control unit 16 which controls the data input / output of the upper data bus 13.

The operation of this embodiment having the above-mentioned structure will be described below with reference to the timing charts shown in FIGS. 3 and 4. 3 is a time chart for memory write access, and FIG. 4 is a time chart for memory read access. When performing write access from the upper CPU 1 to the lower shared memory 11, (1) the shared memory address register 20 of the bus conversion circuit 4
In response, the upper CPU 1 sets the shared memory address value. An I / O address is assigned to the shared memory address register 20, and the address output from the upper CPU 1 is input to the bus conversion circuit 4 from the upper address bus 14 and decoded by the I / O address decoding unit 17. . The I / O address decoding unit 17
The shared memory address register select signal 18 is output according to the input address value. At this time, the data input from the upper data bus 13 is transferred to the shared memory address register 2 by the upper input / output instruction control signal 15.
Set to 0.

(2) After setting the address in the shared memory address register 20, the upper CPU 1 performs a data write operation to the shared memory data register 21 of the bus conversion circuit 4. The shared memory data register 21 has an I / O
Address is assigned, and upper address bus 1
The I / O address decoding unit 17 outputs the shared memory data register select signal 19 based on the address input from No. 4. The timing control unit 24 outputs the shared memory data register latch signal 26 in response to the shared memory data register select signal 19 and the upper side input / output instruction control signal 15, and at this time, outputs the data input from the upper side data bus 13. Set in the shared memory data register 21. Thereafter, the timing controller 24 outputs the lower address bus controller control signal 28, and outputs the value of the shared memory address register 20 to the lower address bus 32. Subsequently, the timing control unit 24 outputs the lower side data bus control unit control signal 27, outputs the value of the shared memory data register 21 to the lower side data bus 31, and then outputs the lower side memory access control signal 29. The value of the shared memory data register 21 is written in the shared memory 11 through the shared memory control unit 9 and the shared memory bus 10.

(3) After writing the value of the shared memory data register 21 to the shared memory 11, the timing control unit 24
Is a shared memory address register count-up signal 25
Is output, the set value of the shared memory address register 20 is counted up, and the write access from the upper CPU 1 to the lower shared memory 11 is completed. Also,
When the upper CPU 1 makes a write access to a continuous area of the shared memory 11, first, the start address of the continuous area is set in the shared memory address register 20 by the process of (1). After that, by repeating the processes (2) and (3) and omitting the process (1), the time required for access can be shortened. Next, a case where the upper CPU 1 makes a read access from the lower shared memory 11 will be described. (4) Similar to the above-mentioned process (1), the host CPU 1 transfers the shared memory address register 20 of the bus conversion circuit 4 to
Set the shared memory address value.

(5) After setting the address for the shared memory address register 20, the upper CPU 1 performs a data read operation to the shared memory data register 21 of the bus conversion circuit 4. The shared memory data register 21 has an I / O
Address is assigned, and upper address bus 1
The I / O address decoding unit 17 uses the address input from the
Is output. The timing control unit 24 outputs the lower side address bus control unit control signal 28 in response to the shared memory data register select signal 19 and the upper side input / output instruction control signal 15, and sets the value of the shared memory address register 20 to the lower side address bus 32. Output to. After that, the timing control unit 24 outputs the lower memory access control signal 29 and reads the value of the shared memory 11 through the shared memory bus 10 and the shared memory control unit 9. Subsequently, the timing control unit 24 causes the shared memory data register latch signal 2
6 is output. At this time, after the data input from the lower data bus 31 is set in the shared memory data register 21, the upper data bus control unit control signal 30 is output and the upper CPU 1 changes the value of the shared memory data register 21. read.

(6) After the upper CPU 1 reads the value of the shared memory data register 21, the timing controller 24 outputs the shared memory address register count up signal 25 to count up the set value of the shared memory address register 20. , Shared memory 1 on the lower side of the upper CPU 1
The read access from 1 is completed. Also, the upper CPU
When 1 performs read access from the continuous area of the shared memory 11, first, the start address of the continuous area is set in the shared memory address register 20 by the processing of (4). After that, by repeating the processing of (5) and (6) and omitting the processing of (4), the time required for access can be shortened. By the above operation,
It becomes possible to access the shared memory of an adapter having an EISA bus or an upper CPU bus different from the ISA bus.

According to the above-described embodiment, the EISA bus or the communication control adapter having an upper CPU bus different from the ISA bus is directly connected to the EISA bus or the ISA bus to access the shared memory of the communication control adapter. Since it becomes possible, the circuit of the communication control adapter having the upper CPU bus different from the already developed EISA bus or ISA bus is diverted to
A new development of a communication control adapter having an A bus or an ISA bus can be carried out easily in a short period of time, development cost can be reduced, and an increase in the amount of hardware can be suppressed to a low level. As a result, it is possible to obtain the effect that the communication control adapter can be downsized and the manufacturing cost can be reduced. It is needless to say that the above embodiment shows one example of the present invention, and the present invention should not be limited to this. For example, the communication control adapter is an example, and the present invention can be applied to various other input / output packages.

[0014]

As described above in detail, according to the present invention, in a shared memory type input / output package having a certain upper CPU bus (B), a bus different from the above.
The bus conversion circuit connected to (A) can be simplified to reduce the physical quantity, and when the shared memory is continuously accessed,
This is a remarkable effect that a bus conversion system can be realized which makes it unnecessary to specify an address value from a host CPU and shortens the time required for shared memory access.

[0015]

[Brief description of drawings]

FIG. 1 is an overall configuration diagram of a communication control adapter showing an embodiment of the present invention.

FIG. 2 is a diagram showing a detailed configuration of a bus conversion circuit which is a main part of the communication control adapter of the embodiment.

FIG. 3 is a time chart at the time of memory write access of the bus conversion circuit of the embodiment.

FIG. 4 is a time chart at the time of memory read access of the bus conversion circuit according to the embodiment.

[Explanation of symbols]

1: Upper CPU, 2: Upper EISA / ISA bus,
3: communication control adapter, 4: bus conversion circuit, 5: lower non-EISA / ISA bus, 6: local CPU, 7: local CPU bus, 8: ROM, 9: shared memory control unit, 10: shared memory bus, 11: shared memory, 12:
Communication control unit, 16: upper data bus control unit, 17: I
/ O address decoding unit, 20: shared memory address register, 21: shared memory data register, 22: lower side data bus control unit, 23: lower side address bus control unit, 24: timing control unit.

Claims (4)

[Claims] 1. A shared memory type input / output package having a certain upper CPU bus (B), which is different from the above bus.
A unit for converting an input / output command for the input / output package from the upper CPU having (A) into a shared memory access in the input / output package is provided, and the input / output package is connected to the bus ( A bus conversion system characterized by being connected to A). 2. In addition to the conversion means, means for updating the address value of the shared memory output by the conversion means each time the shared memory is accessed in the input / output package from the upper CPU is provided. Bus conversion system. 3. The conversion means decodes an address in an input / output instruction for the input / output package and distributes the address to the shared memory address register and the data register, and the setting of the address register selected by the distribution means. 3. A means for converting an input / output instruction for the data register into the shared memory access based on a value.
Bus conversion system described. 4. The bus conversion system according to claim 2, wherein the updating unit is constituted by a count-up unit of the shared memory address register.