JPH02127750A - 16-bit dma data transfer circuit - Google Patents

Abstract

PURPOSE:To realize the transfer of DMA data for each byte or word by providing a DMA data control circuit which activates an address latch circuit and a bidirectional buffer circuit for each byte or word. CONSTITUTION:A microprocessor, a DMA controller, and an input/output device are connected to an address data bus 23, and a high-order data bus 21 is connected to a high-order byte of a memory. At the same time, a low-order data bus 22 is connected to a low-order byte of the memory. A DMA data control circuit 6 identifies the data transfer mode based on the control signal received from the microprocessor or the DMA controller and gives the enable signals to the corresponding address latch circuits 1 and 5, and bidirectional buffer circuits 2 - 4 to activate these circuits for each byte or word. Thus the DMA data can be transferred for each byte or word.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention is applied to a 16-bit DMA data transfer circuit for DMA data transfer. In particular, the present invention relates to a 16-bit DMA data transfer circuit that enables data transfer between a memory and an input/output device on a byte-by-byte and word-by-word basis.

〔overview〕

In a 16-bit DMA data transfer circuit, the present invention identifies whether byte data transfer or word data transfer is performed by a microprocessor or DMA based on an input control signal, and based on the discrimination result, the corresponding address latch circuit and bidirectional buffer are transferred. By activating the circuit, DMA data transfer can be performed in either byte units or word units.

[Conventional technology]

Conventionally, 16-bit DMA data transfer circuits have been processing circuits that process only in byte units or processing circuits that process only in word units.

[Problem that the invention seeks to solve]

However, in such a conventional 16-bit DMA data transfer circuit, the DMA data transfer circuit in both byte units and word units
There was a drawback that MA data transfer was not possible.

The present invention solves the above-mentioned drawbacks and is capable of DMA data transfer in either byte or word units.
The object of the present invention is to provide a 6-bit DMA data transfer circuit.

[Means for solving problems]

In a DMA data transfer circuit, the present invention identifies a data transfer mode based on a control signal from a microprocessor or a DMA controller, and provides an enable signal to a corresponding address latch circuit and bidirectional buffer circuit based on the identification result. The present invention is characterized in that it includes a DMA data control circuit that activates both lever circuits in units of bytes or units of words.

[Effect]

DMA data control circuit is microprocessor or DM
The data transfer mode is identified based on the control signal from the A controller, and based on the identification result, an enable signal is given to the corresponding address latch circuit and bidirectional buffer circuit to activate both circuits in byte units or word units. Make it. This allows DMA data transfer in either byte or word units.

〔Example〕

Embodiments of the present invention will be described with reference to the drawings. 1st
The figure is a block diagram of a 16-bit DMA data transfer circuit according to an embodiment of the present invention. The address latch signal 2 is inserted between the address data bus 23 and the address bus 20 and is sent from the microprocessor as a first address latch signal.
Address latch circuit 1 is inserted between address data bus 23 and address bus 20 and inputs address latch signal 26 as a second address latch signal from the DMA controller. an address latch circuit 5 as an address latch circuit, a bidirectional buffer circuit 2 as a first bidirectional buffer circuit inserted between the upper side of the address data bus 23 and the upper side data bus 21, and the address data bus 23. A second bidirectional buffer circuit 3 is inserted between the upper side of the address data bus 23 and the lower side data bus 22, and a second bidirectional buffer circuit is inserted between the lower side of the address data bus 23 and the lower side data bus 22. A bidirectional buffer circuit 4 is provided as a third bidirectional buffer circuit. A direction control signal is inputted to the bidirectional buffer circuits 2 to 4 from a microprocessor or a DMA controller.

The feature of the present invention is that the data transfer mode is identified based on a control signal from a microprocessor or DMA controller, and based on the identification result, an enable signal is sent to the corresponding address latch circuit and bidirectional buffer circuit. Microprocessor address control signal 100, DMA address control signal 104, upper data control signal 101, and lower data control signal 10
The present invention is provided with a DMA data control circuit 6 which applies a corresponding control signal of 2.103 to activate the state in units of bytes or units of words.

FIG. 2 shows D of the 16-bit DMA data transfer circuit of the present invention.
FIG. 2 is a block diagram of an MA data control circuit.

In Figure 2, 10 is an OR circuit, 1! is a Nando circuit,
12 is a three-man NAND circuit, 13 is an AND circuit, 14 is an inverter circuit, 30 is a byte high enable signal, 31
is the address AO signal, 32 is the data enable signal, 3
Reference numeral 3 designates an interoperable actuator signal, 34 a chip select signal, and 35 an address enable signal.

In FIG. 1, a microprocessor, a DMA controller, and an input/output device are connected to the address data bus 23, an upper data bus 21 is connected to the upper byte of the memory, and a lower data bus 22 is connected to the lower byte of the memory. It has been followed. Furthermore, in the case of a 16-bit microprocessor, the address is 20 to 24 bits, and in order to save the number of pins, it is used as both a data bus and an address bus. Therefore, an address latch circuit 1.5 is provided to separate the address from the address data bus 23.

The operation of the 16-bit DMA transfer circuit having such a configuration will be explained. Table 1 is a table showing modes corresponding to input signals of the DMA data control circuit of the 16-bit DMA transfer circuit of the present invention. Table 2 shows the 16-bit DMA of the present invention.
3 is a table showing output signals corresponding to human input signals of the DMA data control circuit of the transfer circuit.

(Hereinafter referred to as the margin of this page) In Figure 1, Figure 2, Table 1 and Table 2, DMA
For lower byte data transfer, the inputs in Table 1 are given, and the logic shown in Table 2 is output. That is, the first
Bidirectional buffer circuit 4 and address latch circuit 5 shown in the figure
becomes active, and lower byte data transfer by DMA becomes possible.

For upper byte data transfer by DMA, the inputs shown in Table 1 are given, and the logic shown in Table 2 is output. That is, the bidirectional buffer circuit 3 and address latch circuit 5 shown in FIG. 1 become active, and upper byte data transfer by DMA becomes possible.

For word data transfer by DMA, the inputs shown in Table 1 are given, and the logic shown in Table 2 is output.

That is, the bidirectional buffer circuit 2, bidirectional buffer circuit 4, and address latch circuit 5 shown in FIG. 1 become active, and word data transfer by DMA becomes possible.

The lower byte data transfer by the microprocessor is
The inputs in Table 1 are given and the logic shown in Table 2 is output. That is, the address latch circuit 1$ and the bidirectional buffer 4 shown in FIG. 1 become active, allowing the microprocessor to transfer lower byte data.

The upper byte data transfer by the microprocessor is
The inputs in Table 1 are given and the logic shown in Table 2 is output. That is, the address latch circuit 1 and bidirectional buffer circuit 2 shown in FIG. 1 become active, allowing the microprocessor to transfer upper byte data.

For word data transfer by the microprocessor, the inputs shown in Table 1 are given, and the logic shown in Table 2 is output. That is, the address latch circuit 1, bidirectional buffer circuit 2, and bidirectional buffer circuit 4 shown in FIG. 1 become active, and word data transfer by the microprocessor becomes possible.

Note that the direction control signal 25 controls the address data bus 23, the upper data bus 21, and the lower data bus 2.
Controls the direction of data transfer between 2 and 2.

〔Effect of the invention〕

As described above, the present invention has the excellent effect of being able to transfer 16-bit DMA data in either byte units or word units.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a 16-bit DMA data transfer circuit according to an embodiment of the present invention. FIG. 2 shows D of the 16-bit DMA data transfer circuit of the present invention.
FIG. 3 is a block configuration diagram of an MA data control circuit. 1.5...Address latch circuit, 2-4...Bidirectional buffer circuit, 6...DMA data control circuit, 10.
...OR circuit, 11...NAND circuit, 12...3 manual NAND circuit, 13...AND circuit, 14...inverter circuit, 20...address bus, 21...upper side data bus , 22... lower side data bus, 23...
・Address data bus, 24...Address latch signal from the microprocessor, 25...Direction control signal,
26... Address latch signal from DMA controller, 30... Byte high enable signal, 31...
Address AO signal, 32... data enable signal,
33...Interactive action ridge signal, 34...
Chip select signal, 35...Address enable signal, 100...Microprocessor address control signal, 101...Upper side data control signal, 102.103
. . . Lower side data control signal, 104 . . . DMA address control signal. Fig. Embodiment DMA data control circuit Fig. 2

Claims (1)

[Claims] 1. A first address latch circuit inserted between an address data bus and an address bus and inputting a first address latch signal from a microprocessor; and between the address data bus and the address bus. a second address latch circuit inserted into the DMA controller and inputting a second address latch signal from the DMA controller; and a first bidirectional buffer circuit inserted between the upper side of the address data bus and the upper side data bus. , a second bidirectional buffer circuit inserted between the upper side of the address data bus and the lower side data bus; and a second bidirectional buffer circuit inserted between the lower side of the address data bus and the lower side data bus. A 16-bit DMA data transfer circuit comprising three bidirectional buffer circuits, which identifies a data transfer mode based on a control signal from the microprocessor or the DMA controller, and a corresponding address latch circuit based on the identification result. and a DMA data control circuit that applies an enable signal to the bidirectional buffer circuit to activate both circuits in units of bytes or units of words.