JPH06149727A - Data bus - Google Patents

Abstract

PURPOSE:To enable plural bus masters to access bus slaves at the same time by providing a data bus, where the bus maters are connected, with a bus opening and closing means and a bus opening/closing control means which controls the bus opening and closing means. CONSTITUTION:A microprocessor 2 uses data bus sections 34 and 35 and data bus sections 32, 33, and 36 are electrically separated from the data bus sections 34 and 35. Therefore, a microprocessor 1 can access a memory 4 through the data bus section 32 and a memory 5 through the data bus sections 32 and 33, and a microprocessor 3 can access a memory 8 through the data bus section 36. The data bus is divided into the data bus sections 32-36 by bus switches 26-29, which can be separated and connected mutually corresponding to address signals outputted from the respective bus masters, so that plural bus masters can access the bus slaves at the same time.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data bus to which a plurality of bus masters are connected.

[0002]

2. Description of the Related Art In recent years, in order to improve the performance of a digital signal processing device, a plurality of microprocessors and DSPs (Digital Signal processes) are used.
sor), DMA (Direct Memory Ac)
Bus masters such as control circuits have been increasingly used.

A conventional data bus will be described below with reference to the drawings. FIG. 9 is a block diagram of a circuit using a conventional data bus. In FIG. 9, 1 to 3 are microprocessors, 4 to 8 are memories, 9 is an input port,
Reference numeral 10 is an output port, and 11 and 12 are address selectors. 13 is a bus arbiter. In general, the bus arbiter 13 has a circuit configuration that controls so as to grant the bus use right according to the priority given to the microprocessors 1 to 3. Further, 14 is an 8-bit data bus, and 15 to 17 are 20-bit address buses output from each of the microprocessors 1 to 3. 18-2
Reference numeral 0 is a bus use right request signal line of the data bus 14 output from each of the microprocessors 1 to 3, and reference numerals 21 to 23 are data buses 1 output from the bus arbiter 13 as a result of arbitration.
4 is a bus use permission signal line.

The address selector 11 inputs the bus use permission signal lines 21 and 22 and the address buses 15 and 16 and generates a memory address 24 which the memory 5 inputs. The address selector 11 inputs the bus use permission signal lines 22 and 23 and the address buses 16 and 17, and generates the memory address 25 input to the memory 7. Of the memories 4 to 8, the memories 4, 6 and 8 are dedicated program memories of the microprocessors 1 to 3 and are not accessed by other microprocessors. The memory 5 is a buffer memory for data transfer between the microprocessors 1 and 2, and is a shared memory that both microprocessors can access. Similarly, the memory 7 is a microprocessor 2, 3
It is a buffer memory for passing data between and is a shared memory that both microprocessors can access.

The operation of the conventional data bus configured as described above will be described below. First, the overall operation of the circuit of FIG. 9 will be described. The circuit shown in FIG. 9 performs three-stage conversion processing on the data input from the input port 9 by the microprocessors 1 to 3 and outputs the resulting data from the output port 10. The microprocessor 1 performs the first conversion process on the data input from the input port 9 according to the program in the memory 4, and writes the resulting data in the memory 5. The microprocessor 2 performs the second conversion process on the data read from the memory 5 according to the program in the memory 6, and writes the resulting data in the memory 7. Microprocessor 3
Performs a third conversion process on the data read from the memory 7 according to the program in the memory 8 and outputs the resulting data to the output port 10.

Next, as an example of the bus slave access operation of the microprocessors 1 to 3, the operation of the microprocessor 2 writing data in the memory 7 will be described. First, the microprocessor 2 outputs a bus use right request signal to the bus arbiter 13 in order to obtain the use right of the data bus 14. The bus arbiter 13 considers the priority order of other microprocessors requesting to use the bus,
The bus use permission signal is output at an appropriate time to give the bus use permission to the microprocessor 2. After this, the microprocessor 2 outputs a signal to the address bus 16 and the data bus 14. The address selector 12 supplies the memory address input to the memory 7. Since the memory 7 can be accessed by both the microprocessors 2 and 3, the address selector 12 determines from the bus use permission signal that the currently valid bus master is the microprocessor 2, and the content of the address bus 16 is changed to the memory address. Output as 25.

As described above, in the conventional data bus to which a plurality of bus masters are connected, the data bus use right is distributed to each bus master on a time-division basis under the arbitration of the bus arbiter 13. FIG. 10 is a diagram showing a time transition of a memory access operation of a microprocessor in a circuit adopting such a data bus. Here, the unit time required for one memory access is T. In this example, 3
It takes 6T for each of the microprocessors 1 to 3 to access the memory twice.

[0008]

However, in the above-mentioned conventional data bus, while one bus master is using the data bus, the other bus masters wait for the data bus to be vacant, which lowers the processing efficiency of the entire circuit. There was a problem of doing.

It is an object of the present invention to solve the above problems and provide a data bus that can be used by a plurality of bus masters at the same time.

[0010]

In order to achieve the above object, the present invention provides a data bus to which a plurality of bus masters are connected with bus opening / closing means and bus opening / closing control means for controlling the bus opening / closing means. Is.

[0011]

According to the present invention, with the above configuration, a data bus to which a plurality of bus masters are connected is divided into a data bus section dedicated to each bus master and a data bus section shared by the pair of bus masters adjacent on the wiring. Based on the address signal and / or status signal output by the bus master, it is possible to divide or connect the adjacent data bus sections, so that multiple bus masters can access the bus slaves at the same time. As a result, the data bus use turn waiting time that occurs when accessing the bus slave can be reduced, so that the processing efficiency of the entire circuit can be improved.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of this embodiment. In FIG. 1, the same components as those shown in FIG. 9 are designated by the same reference numerals and described. 26 to 29 are bus switches, and 30 and 31 are bus switching controllers. Also,
Reference numerals 32-36 denote data bus sections in which the data buses are divided by the bus switches 26-29. Data bus section 32
To 36, the data bus sections 32, 34, and 36 are dedicated data bus sections for the microprocessors 1 to 3, and the data bus section 33 is the microprocessors 1 and 2.
Is a shared data bus section, and the data bus section 35 is a shared data bus section of the microprocessors 2 and 3. Reference numerals 37 to 39 are bus status signal lines indicating the contents of bus access such as reading and writing output from each of the microprocessors 1 to 3. The microprocessors 1 to 3 output an L level signal to the respective bus status signal lines 37 to 39 when performing a read operation, and otherwise output an H level signal.

Reference numeral 40 denotes a bus use right request signal line of the data bus section 33 which the microprocessor 1 outputs to the microprocessor 2, and 41 denotes a data bus section 3 which the microprocessor 2 outputs to the microprocessor 1.
3 is a bus use permission signal line. 42 is a bus use right request signal line of the data bus section 33 which the microprocessor 2 outputs to the microprocessor 1, and 43 is a bus use permission signal of the data bus section 33 which the microprocessor 1 outputs to the microprocessor 2. It is a line. Four
4 is a bus use right request signal line of the data bus section 35 output from the microprocessor 2 to the microprocessor 3, and 45 is a bus use permission signal of the data bus section 35 output from the microprocessor 3 to the microprocessor 2. It is a line. Reference numeral 46 is a bus use right request signal line of the data bus section 35 which the microprocessor 3 outputs to the microprocessor 2, and 47 is the microprocessor 2
Is a bus use permission signal line of the data bus section 35 which is output to the microprocessor 3.

FIG. 2 is an internal block diagram of the bus switch 26 of this embodiment. The terminal V is a power supply terminal of the bus switch 26, and the terminal GND is a ground terminal of the bus switch 26. A1 to A8 and B1 to B8 are terminals for connecting a data bus, and the data bus section 3 is connected to the terminals A1 to A8.
2 is connected, and the data bus section 33 is connected to the terminals B1 to B8. The terminal EN is an input terminal for output enable signals of the terminals A1 to A8 and the terminals B1 to B8. While the input signal of the terminal EN is at L level, the terminals A1 to A8 or the terminals B1 to B8
One of B8 serves as an input terminal and the other serves as an output terminal, and the data bus sections 32 and 33 are electrically connected.
Further, while the input signal of the terminal EN is at H level, all the terminals A1 to A8 and B1 to B8 for data bus connection are in a high impedance state, and the data bus sections 32 and 33 are electrically divided.

The terminals DR are terminals A1 to A8 and terminals B1 to B.
8 is an input terminal for a data input / output direction specifying signal.
While the input signal of the terminal DR is at the L level, the terminals B1 to B
8 is an input terminal, terminals A1 to A8 are output terminals, and the data input at terminals B1 to B8 are output to terminals A1 to A8. Further, while the input signal of the terminal DR is at H level,
The terminals A1 to A8 are input terminals, the terminals B1 to B8 are output terminals, and the data input at the terminals A1 to A8 are terminals B1 to B1.
It is output to B8. FIG. 3 is a table in which the operating states of the bus switch 26 according to the input signals of the terminals EN and DR are arranged. The bus switches 27 to 29 have the same structure as the bus switch 26.

FIG. 4 is a memory map of each of the microprocessors 1 to 3 shown in FIG. The memory address space of the microprocessor 1 has memories 4 and 5, and the memory address space of the microprocessor 2 has memories 5 to 5.
7, the memories 7 and 8 are allocated to the memory address space of the microprocessor 3.

FIG. 5 is a block diagram showing the internal structure of the bus opening / closing controller 30 shown in FIG. DR0, EN
0 is a data input / output direction designating signal line and an output enabling signal line for the bus switch 26, and DR1, EN1
Are a data input / output direction designating signal line and an output enabling signal line for the bus switch 27, respectively. MA1 is memory 5
Is a 17-bit memory address signal line to be input.
48 is an address decoder for the upper 3 bits of the 20 bits of the address bus AB0, and E0 is an output signal line of the address decoder 48. The address decoder 48 outputs AB0 when the microprocessor 1 outputs an address signal of the memory 5, that is, an address signal of [00000H] to [1FFFFH] (H at the end indicates hexadecimal notation) to the address bus AB0. Top 3
It is detected that the bit has become [000B] (B at the end indicates that it is a binary number expression), and the output signal line E0 is detected.
To L level. In other cases, the output signal line E0 is always at H level.

Reference numeral 49 is an address decoder for the upper 3 bits of the 20 bits of the address bus AB1.
E1 is an output signal line of the address decoder 49. In the address decoder 49, the microprocessor 2 has a memory 5
Address of [20000H] to [3FFFFH]
When the address signal is output to the address bus AB1, it is detected that the upper 3 bits of the address bus AB1 have become [001B], and the output signal line E1 is set to the L level.
At all other times, the output signal line E1 is always at H level. A memory address selector 50 receives the lower 17 bits of the address bus AB0 and the lower 17 bits of the address bus AB1 and selects which is to be the memory address signal line MA1.

Reference numeral 51 is a bus open / close determiner for generating the output enable signal line EN0 of the bus switch 26 from the output signal lines E0 and E1 of the address decoders 48 and 49, and 52 is the output enable signal line EN0 and the bus status. It is a bus direction determiner that generates a data input / output direction specifying signal line DR0 of the bus switch 26 from the signal RW0. Reference numeral 53 is a bus open / close determiner that generates the output enable signal line EN1 of the bus switch 27 from the output signal lines E0 and E1 of the address decoders 48 and 49, and 54 is from the output enable signal line EN1 and the bus status signal RW1. It is a bus direction determiner that generates a data input / output direction specifying signal line DR1 of the bus switch 27.

FIG. 6 shows the bus opening / closing controller 3 shown in FIG.
2 is a block diagram showing the internal configuration of No. 1. DR2, EN2
Are data input / output direction designating signal lines and output enabling signal lines for the bus switch 28, and DR3 and EN3 are data input / output direction designating signal lines and output enabling signal line for the bus switch 29, respectively. Is a 17-bit memory address signal line input to the memory 7. Further, 55 is an address decoder for the upper 3 bits of the address bus AB1, and E2 is an address decoder 55.
Is an output signal line of. In the address decoder 55, the microprocessor 2 addresses the memory 7, that is, [40000
When the address signals of [H] to [5FFFFH] are output to the address bus AB1, the upper 3 bits of AB1 are [010
B] is detected, and the output signal line E2 is set to L level. At all other times, the output signal line E2 is always at the H level. Reference numeral 56 is an address decoder for the upper 3 bits of the address bus AB2, and E3 is an output signal line of the address decoder 56. In the address decoder 56, the microprocessor 3 addresses the memory 7, that is, [0
When an address signal of 0000H] to [1FFFFH] is output to the address bus AB2, it is detected that the upper 3 bits of AB2 have become [000B], and the output signal line E3
To L level. Otherwise, the output signal line E3 is always at H level.

57 is the lower 17 bits of AB1 and AB
A memory address selector that inputs the lower 17 bits of 2 and selects which is used as the memory address signal line MA3, and 58 is an output valid of the bus switch 28 from the output signal lines E2 and E3 of the address decoders 55 and 56. A bus open / close determiner for generating the activation signal line EN2, and a bus direction determiner 59 for generating the data input / output direction designating signal line DR2 of the bus switch 28 from the output validation signal line EN2 and the bus status signal RW1. Further, 60 is an address decoder A
From the output signal lines E2 and E3 of D2 and AD3 to the bus switch 2
A bus open / close determiner for generating the output enable signal line EN3 of 9 and a bus direction determiner for generating the data input / output direction designating signal line DR3 of the bus switch 29 from the output enable signal line EN3 and the bus status signal RW2. Is.

The operation of the data bus configured as described above will be described below. First, the overall operation of the circuit of FIG.
The microprocessors 1 to 3 perform conversion processing in three stages, and the resulting data is output from the output port 10. At this time, the memories 5 and 7 are used as buffer memories for passing data between the microprocessors.

Next, as an example of the bus slave access operation of the microprocessor, the operation of the microprocessor 2 writing data in the memory 7 will be described. FIG. 7 is a flowchart showing a series of operations when the microprocessor 2 writes data in the memory 7.
The signals transmitted by the bus use right request signal lines 44 and 46 and the bus use permission signal line 45 will be described with reference to FIG. 7. The data bus section 35 may be used by both the microprocessors 2 and 3. Therefore, the bus use right request signal lines 44 and 46 and the bus use permission signal line 45,
47 is used to prevent use by both microprocessors at the same time.

Before accessing the memory 7, the microprocessor 2 confirms that the signal on the bus use right request signal line 46 is at H level, that is, the microprocessor 3 is not using the data bus section 35. If the signal on the bus use enable signal line 45 is at L level, the microprocessor 3 finishes using the data bus section 35 and waits for the signal on the bus use enable signal line 45 to go to H level. After that, the microprocessor 2 sets the signal on the bus use right request signal line 44 to the L level to set the data bus section 35.
After requesting the right to use the signal, the microprocessor 3 permits this request, waits for the signal on the bus use permission signal line 45 to go to the L level, and then the address bus AB1, the bus status signal line 38, and the data bus. Output a signal. After that, the microprocessor 2 receives the bus right request signal line 44.
Signal is set to H level, the right to use the data bus section 33 is abandoned, and then a series of write operations ends. The microprocessor 3 responds to this by using the bus use permission signal line 4
The permission is canceled by setting the signal of 5 to the H level.

The operation when signals are output to the address bus AB1, bus status signal RW1 and data bus DB in FIG. 7 will be described below. According to the memory map of FIG. 4, the memory 7 has a memory space of [400
It is assigned to addresses 00H] to [5FFFFH]. Therefore, the microprocessor 2 uses the address bus AB
1 is one address in this range, eg [5000
[0H] is output, and an H level signal is output as the bus status signal RW1. Bus opening / closing controller 30 shown in FIG.
And 31 input these signals. In FIG. 5, since the upper 3 bits of the address bus AB1 is [010B], the output signal line E1 of the address decoder 49 becomes H level and the output signal EN1 of the bus open / close determiner 53 becomes H level. Therefore, the terminal E of the bus switch 27 shown in FIG.
An H level signal is input to N, and terminals A1 to A8, B
1 to B8 are in a high impedance state, and the data bus sections 33 and 34 of FIG. 1 are divided. At the same time, in FIG. 6, the upper 3 bits of the address bus AB1 are [010B].
Therefore, the output signal line E2 of the address decoder 55 is L
It becomes a level.

On the other hand, in FIG. 1, the bus use permission signal line 4
During the period when 5 is at the L level, the microprocessor 3 has the memory 7
, The upper 3 bits of the address bus AB2 never become [000B], and the output signal E3 of the address decoder AD3 maintains the H level. Therefore, in FIG. 6, the output signal EN2 of the bus open / close determiner 58 is output.
Goes to L level, and the output signal DR2 of the bus direction determiner 59 goes to H level. Therefore, the bus switch 2 of FIG.
The signal of L level is input to the terminal EN of 8 and the terminal DR
An H level signal is input to. Therefore, from the table shown in FIG. 3, the data input from the terminals A1 to A8 of the bus switch 28 is output to the terminals B1 to B8, and the data bus sections 34 and 35 are connected.

On the other hand, in FIG. 6, the output signal E3 of the address decoder 56 of the bus open / close controller 31 is at the H level as described above, and therefore the output signal EN of the bus open / close determiner 60.
3 becomes H level. Therefore, an H level signal is input to the terminal EN of the bus switch 29 of FIG.
The terminals A1 to A8 and B1 to B8 of 9 are in a high impedance state, and the data bus sections 35 and 36 are divided.

As described above, the microprocessor 2 uses the data bus sections 34 and 35, but does not use the data bus sections 32, 33 and 36, and the data bus sections 34 and 35 are electrically connected. Are separated. Accordingly, in parallel with the above operation, the microprocessor 1 accesses the memory 4 via the data bus section 32 or the memory 5 via the data bus sections 32 and 33.
, And the microprocessor 3 can access the memory 8 via the data bus section 36.

As described above, according to this embodiment, the data bus is connected to the data bus section 32 to 32 by the bus switches 26 to 29.
The data bus sections can be separated or connected in accordance with the address signal output from each bus master, so that a plurality of bus masters can access the bus slaves at the same time, and the entire circuit can be accessed. The processing efficiency of can be improved. This will be described with reference to FIGS. 8 and 10. FIG. 8 shows the time transition of the memory access operation of the microprocessor in the circuit of this embodiment. Here, the unit time required for one memory access is T. Here, FIG.
The same memory access as in 2 is completed in 2T. In this way, since the data bus DB use order waiting time that occurs when accessing the bus slave can be reduced, the processing efficiency of the entire circuit can be improved. In addition, the bus arbiter circuit is configured so that the usage right of the data bus section shared by the two microprocessors is transmitted and received using the bus usage right request signal line and the bus usage permission signal line that are provided between the microprocessors. It can be omitted.

[0030]

According to the present invention, a data bus to which a plurality of bus masters are connected is provided with bus opening / closing means and bus opening / closing control means for controlling the bus opening / closing means, and the data bus is dedicated to each bus master. It is divided into a section and a data bus section shared by adjacent bus master pairs on the wiring.
Based on the address signal and / or status signal output by the bus master, it is possible to divide or connect adjacent data bus sections, so that multiple bus masters can access the bus slaves at the same time. Since it is possible to reduce the data bus use turn waiting time that occurs when accessing the bus slave, it is possible to realize an excellent data bus that can improve the processing speed of the entire circuit.

[Brief description of drawings]

FIG. 1 is a block diagram of a circuit using a data bus according to an embodiment of the present invention.

FIG. 2 is an internal block diagram of a bus opening / closing means of the data bus.

FIG. 3 is a diagram showing an operating state of a bus opening / closing means of the data bus.

FIG. 4 is a diagram showing a memory map of each microprocessor connected to the data bus.

FIG. 5 is an internal block diagram of bus opening / closing control means of the data bus.

FIG. 6 is an internal block diagram of bus opening / closing control means of the data bus.

FIG. 7 is a flowchart of a write operation of the microprocessor of the data bus.

FIG. 8 is a diagram showing a time transition of a memory access operation of the microprocessor of the data bus.

FIG. 9 is a block diagram of a circuit using a conventional data bus.

FIG. 10 is a diagram showing a time transition of a memory access operation of the microprocessor of the data bus.

[Explanation of Codes] 1,2,3 Microprocessor 4, 5, 6, 7, 8 Memory 9 Input Port 10 Output Port 26, 27, 28, 29 Bus Switch 30, 30 Bus Switch Controller

Claims (1)

[Claims] 1. A bus opening / closing means for dividing a data bus to which a plurality of bus masters are connected into a plurality of sections, and an address signal or a status signal output by the bus master or both of them to control the bus opening / closing means. Bus opening / closing control means for dividing the data bus into a data bus section dedicated to each of the bus masters and a data bus section shared by the pair of bus masters adjacent in wiring, and the bus opening / closing control means is provided. A data bus capable of dividing or connecting adjacent data bus sections by controlling the bus opening / closing means.