KR0141288B1 - Redundant control unit with internal bus extension - Google Patents

Abstract

The present invention relates to a redundant control device of a memory sharing type applied to a communication system such as an electronic switch.

To this end, the present invention, in the control device having a dual control module having a CPU and a memory module, each control module acts as the input and output ports of the CPU and the first and second buffers, the internal and external ports of the memory module And a third buffer, an internal bus connecting the first buffer and the CPU, an internal bus arbiter connected to the CPU, a decoder and a memory controller for controlling the first and second buffers to update data of the memory module.

Therefore, the redundant control apparatus according to the present invention has an advantage that the configuration thereof is simple, the design is easy, and the reliability can be improved.

Description

Redundant control unit with internal bus extension

1 and 2 is a block diagram according to the prior art

3 is a block diagram of a control device according to the present invention

* Explanation of symbols for main parts of the drawings

11, 21: CPU 12,22: internal bus arbiter

13, 23: decoder 14, 24: memory control unit

15, 25: Main memory module 16, 17, 18, 26, 27, 28: buffer

19, 29: internal bus

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a redundant control device of a memory sharing type applied to a communication system such as an electronic switch, and more particularly, to a redundant control device having an extended form of an internal bus whose configuration is simpler and the reliability is improved. .

In general, the control device of the electronic switchboard maintains the memory with the same data on the duplicated counterpart every second in a fault tolerance method to improve reliability. It is designed as a redundant structure that operates on the operation side and provides continuity of service.

1 and 2 are block diagrams of a control apparatus having a conventional redundant structure.

FIG. 1 shows the structure of a control device in which the main control modules 1 and 6, the memory modules 2 and 5, and the redundant channel modules 3 and 4 are implemented in redundancy. The three modules of the control module 1, 6, the memory modules 2, 5 for storing a large amount of data, and the redundant channel modules 3, 4 for providing a connection path for redundancy are duplicated.

Modules constituting the control device of one side (hereinafter referred to as A side) are connected through the A bus, and modules constituting the control device of the other side (hereinafter referred to as B side) are connected through the B bus to each other. Send and receive data.

The main control module of the control device on the A side or the control device on the B side must open the C channel in the redundant channel module (3, 4) and connect the A and B buses in order to keep the data the same on the other side. The same must be maintained. The operation for maintaining the sameness of the memory is as follows.

In the above, when the main operation control device is the A side and the standby control device is the B side, the main control module 1 of the A side has the same data in the magnetic memory module 2 and the opposite memory module 5. In order to maintain C, it must occupy C channel and B bus. To occupy this, the B bus is requested to the opposing main control module 6 through the redundant channel module 3. At this time, the main control module 6 allows the occupancy of the B bus when the B bus is not in use. Accordingly, the main control module 1 writes the same data as the memory module 2 to the memory module 5 of the B-side control apparatus via the A bus-C channel-B bus using the occupied B bus.

FIG. 2 shows a configuration more advanced than that of FIG. 1, that is, the C channel in FIG. 1 corresponds to the D channel in the drawing, and through this D channel, CPUs 7 and 8 on the A and B sides. Is able to access the other's memory, and the parts corresponding to the A and B buses of FIG. 1 are the E bus and the F bus in the drawing, which are separated from the D channel, which is a path for accessing the memory from the other side.

The structure of FIG. 2 should be accessed through the buffer a, the buffer b, and the buffer c for the memory module 9, and the buffer a, the buffer e, and the buffer f for the memory module 10. Coordination and arbitration logic is designed so that only one of b, buffer c (or buffer d, buffer e, buffer f) can be accessed. The operation of maintaining memory equality through this coordination and arbitration logic is as follows.

When the main operation part is the A side and the standby state part is the B side, the A side CPU 7 is connected to the B side memory in order to maintain the same data in the A side memory module 9 and the B side memory module 10. Must occupy the memory bus. In order to occupy this, the memory bus is requested to the adjustment circuit on the B side via the path, buffer a → buffer b → buffer d. At this time, the adjustment circuit on the B side grants the possession right when the B side bus is not used. In other words, the CPU 7 on the A side writes data to the path of the buffer a to the memory module 9, and simultaneously writes data to the buffer a to buffer b to the buffer d to the memory module 10. I can keep it.

The prior art as described above is developed in a modular configuration as shown in FIG. 2 by modifying the memory approach to improve economics in the three module types shown in FIG.

However, in the redundancy structure where reliability is the most important factor, the parts that can access the memory are one path through the A bus or the B bus in FIG. 1, and the buffer a, buffer b, and buffer c (buffer d) in FIG. It is composed of three extended structures, buffer e and buffer f, which increases the complexity of adjustment and arbitration circuits and is not easy to design. As a result, reliability is degraded. Focused around. That is, the prior art has a problem in that reliability decreases as the number of accessible parts of the memory increases by increasing the difficulty of the design technology and increasing the complexity of the control part.

Accordingly, an object of the present invention is to provide a redundancy control device configured to be easy to design and to improve reliability.

In order to achieve the above object, a redundant control apparatus having an internal bus extension form according to the present invention is characterized in that each control module includes a memory module and a CPU generating control data for updating data stored in the memory module. In a redundant control device having an internal bus extension type, each control module includes: first and second buffers that function as internal and external ports of the memory module according to control of the CPU; An internal bus connecting the first buffer and the CPU; An internal bus arbitrator connected to the CPU so as to arbitrate the internal bus under the control of the CPU to allow the CPU or the CPU of the counterpart to occupy the internal bus; It is in contact with the internal bus and acts as an output port for transmitting the output data of the CPU to another control module when the CPU is a master, and inputs data provided from the CPU of another control module when the CPU is a slave. A third buffer acting as an input port; When the CPU is a master, the first and second buffers are controlled to update data for a predetermined address of the memory module according to control data for data update provided from the CPU through an internal bus. In the case of a slave, the first and second buffers are controlled in accordance with control data for data update provided from the CPU of the other control module through an internal bus occupied by the CPU of the other control module. It includes a decoder and a memory control unit for updating data for the address.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

3 is a block diagram of a redundant control device according to the present invention.

Referring to FIG. 3, a control device in which control modules each including CPUs 11, 21 and main memory modules 15, 25 are duplicated is used for each control module (A) (B). Buffer 2 and Buffer 3 (16) (17), which are internal and external ports of the module (15) (25), or Buffer 5 and Buffer 6 (26) (27), and Buffer 1 and Buffer 4 (18) connected via C channel. 28, and an internal bus arbiter 12 connected between the CPU 11, 21 and buffers 1 and 4, 18, 28 to arbitrate an internal bus under the control of the CPU 11; 22) and buffers 2 and 6 (16) 26 and CPU 11 (21) and buffers 1 and 4 (18) (28) according to the arbitration of the internal bus arbiter (12) (22). Decoder 13 (23) and memory control unit for controlling buffers 2 and 5 (16) and 26 according to the internal buses 19 and 29 to be connected and the control data output from the CPUs 11 and 21. (14) (24) and mains for updating data at the request of the CPU 11 (21) under the control of the memory controllers 14 (24) through the buffers 2 and 5 (16, 26). Comprises a memory module 15 (25).

Looking at the effect of the present invention configured as described above are as follows.

One of the CPUs 11 and 21 on both sides may become a master by a setting that can be changed in software, and the master CPU 11 and 21 may request the use of an internal bus to the counterpart control module. That is, if the CPU 11 of the A side is the master, data is updated in the magnetic memory module 15 via the internal bus 19-> buffer 2 16, and at the same time, the buffer 1 (18)-> C channel-> buffer. The control signal is output through 4 (28) to request the internal bus arbiter 22 to use the internal bus 29. The local bus arbiter 22 and the CPU 21, which are requested to use the internal bus 29, permit the CPU 11 to use its own internal bus 29 and transition to the idle state.

The CPU 11 occupying the counterpart internal bus 29 transmits control data, that is, a read or write control signal, through the buffer 1 18 and the buffer 4 28, the internal bus 29 and the buffer 5 26. The data is requested to the memory control section 24 by providing the memory control section 24 and providing the initialization signal or the address signal to the decoder 23.

That is, the decoder 23 decodes the initialization signal or address signal provided from the CPU 11 to the memory controller 24, and the memory controller 24 reads or writes the control signal and the initialization signal provided from the decoder 23. Alternatively, the data update request from the CPU 11 is recognized in accordance with the address signal.

Accordingly, the memory controller 24 receiving the memory update request signal such as an initialization signal or an address signal generates a control signal to open the buffer 5 26, block the buffer 6 27, and then correspond to the main memory module corresponding to the address signal. The data is updated by performing initialization or writing to the address in (25).

In addition, when the B-side CPU 21 is the master, data update is performed on the A-side control module in the same process as described above, and thus the description thereof will be omitted.

Therefore, the present invention constructed and operated as described above has a redundant structure in which the master side occupies the CPU internal bus on the slave side in the redundant control device, so that the counterpart resource can be treated like the own side resource, and thus the external bus. Compared with the existing redundancy structure with expansion type, the design is easy and the complexity of control logic can be eliminated, so the integration of logic circuits is easy, so it is more economical and the effect of implementing a reliable redundancy device is achieved.

Claims (1)

A redundant control apparatus having an internal bus extension form in which each control module having a memory module and a CPU for generating control data for updating data stored in the memory module is duplicated, wherein each control module comprises: the CPU; First and second buffers acting as internal and external ports of the memory module according to control of the first and second buffers; An internal bus connecting the first buffer and the CPU; An internal bus arbiter connected to the CPU so as to arbitrate the internal bus under the control of the CPU so that the CPU or the CPU of the counterpart occupies the internal bus; It is connected to the internal bus and acts as an output port for transmitting output data of the CPU to another control module when the CPU is a master, and inputs data provided from the CPU of another control module when the CPU is a slave. A third buffer serving as an input port; When the CPU is a master, the first and second buffers are controlled to update data for a predetermined address of the memory module according to control data for data update provided from the CPU through an internal bus. In the case of a slave, the first and second buffers are controlled in accordance with control data for data update provided from the CPU of the other control module through an internal bus occupied by the CPU of the other control module. A redundant control device including a decoder and a memory control unit for updating data for the address.