KR100395452B1 - Arbitrating Apparatus Of Peripheral Processor And Device In Switching System - Google Patents

Abstract

In the switching system, the matching between the peripheral processor and the device allows the matching device, which consists of redundancy, to share state information, which expands the memory area where data is stored and increases the use efficiency of the matching device that maintains the standby state. To provide speed and stability.

The present invention connects the matching devices to each other through a 'SCC' communication path in a matching device of a redundant structure for data relay between a peripheral processor and a lower level device in a switching system, and jointly occupies a TD-BUS connected to the peripheral processor. It is characterized in that it comprises a mediation device for arbitration.

The arbitration device is configured to control each of the matching devices of the redundant structure so as to exchange state information of the matching device of the opposite side, and receives the TD-BUS occupancy right according to the status change request signal applied from the control means in the matching device. Next, the partner matching device copies data received through the 'SCC' communication path, stores the data in the DPRAM, and communicates with a peripheral processor through the TD-BUS.

Thus, the load of the system is shared, providing efficiency in operation and providing rapid data processing.

Description

Arbitrating Apparatus Of Peripheral Processor And Device In Switching System

The present invention relates to a matching device between a peripheral processor (Peripheral Processor) and a device connected in a switching system, and more particularly, a memory area in which data is stored by sharing state information between matching devices configured as redundancy. This paper relates to an intermediary of peripheral processors and devices in a switching system that provides fast and reliable operation of the system by increasing the efficiency of using a matching device that maintains the standby state.

In a conventional switching system, a matching device between a peripheral processor and a device may include a peripheral processor 10 connected to an upper processor (not shown), a peripheral processor 10 and a TD-BUS, as shown in FIG. 1. It is connected through, consisting of a matching unit 20A (20B) consisting of a redundancy, the matching unit 20A (20B) consisting of a redundancy and a plurality of devices (30A-30N) connected to the IPC, the peripheral The processor 10 is a data processing apparatus using a relay with a matching unit 20A, 20B, which is composed of redundancy through TD-BUS according to the control of an upper processor or an algorithm set to F / W (Firm Ware). It transmits and receives general data processed by the device 30A-30N, and transmits and receives status information and control information.

The matching units 20A and 20B, which are composed of redundancy, are operated in an active and standby manner, communicate with the peripheral processor 10 through the TD-BUS, and the device 30A- which is a data processing apparatus through the IPC. 30N) performs data transmission and reception and control signal relay between the peripheral processor 10 and the device 30A-30B, which is a data processing apparatus.

The matching units 20A and 20B are provided with DPRAM 21A and 21B to store data and control signals transmitted and received between the device 30A-30N, which is a data processing apparatus, and the peripheral processor 10.

In the conventional switching system having the configuration as described above, the operation of performing matching between the peripheral processor and the device is as follows.

When the peripheral processor 10 intends to transmit a control signal or data to the lower-level device 30A-30N, which is a data processing device, according to the control of the upper processor or the algorithm set to the F / W, the TD- Determining the state of matching units 20A and 20B of a redundant structure connected by BUS, recognizing the matching unit 20A that maintains the active state, and then applying the corresponding control signal or data stream to the active state through the TD-BUS. Is stored in the DPRAM 21A of the matching section 20A.

At this time, the processor in the matching unit 20A transmits the control signal or data stream stored in its DPRAM 21A to the corresponding device 30A-30N, which is a data processing apparatus, via the IPC in accordance with the system clock to correspond to the corresponding data. Processing is performed, and the data processing result received from the device 30A-30N through the IPC is stored in the DPRAM 21A so that the peripheral processor 10 connected to the TD-BUS can access the data processing result. do.

Since the matching device between the peripheral processor and the device of the conventional switching system performing the operation as described above communicates with the device, which is a data processing device, only through the matching device in which the peripheral processor remains active among the matching devices in which the peripheral processor is configured to be redundant. In the case of a matching device that is in a standby state, the matching device that is in an active state is always in a standby state when there is no change in external conditions such as power down or malfunction.

Therefore, when the data throughput of the devices processed by the matching device increases, the data throughput of the matching device that remains active increases, thereby increasing the processing capacity of the DPRAM, resulting in a shortage of memory allocation. Therefore, there is a problem of increasing the load on the system due to the delay of the buffer pool and the data processing speed.

The present invention has been made in view of the above-described general problems, and an object thereof is to share state information between matching devices having a redundant structure in order to mediate control signals and data streams between peripheral processors and lower-level devices, which are data processing devices. If the data processing and memory allocation of the matching device is kept active, the data processing and memory allocation is performed through the matching device in the active state. To provide efficiency.

1 illustrates a matching device of a peripheral processor and a device in a conventional exchange system.

2 illustrates an arbitration device of a peripheral processor and a device in a switching system according to the present invention.

Figure 3 is a detailed configuration of the arbitration device between the peripheral processor and the device in the switching system according to the present invention.

4 is a timing diagram for performing data arbitration between a peripheral processor and a device in a switching system according to the present invention.

<Explanation of symbols for the main parts of the drawings>

21A, 21B: DPRAM 22A, 22B: Control part

50A, 50B: Arbitration Department

In accordance with an aspect of the present invention, there is provided a matching device having a redundant structure for data relay between a peripheral processor and a lower level device in an exchange system, wherein the matching device is connected to an 'SCC' communication path, and the peripheral processor is connected. And an arbitration device that arbitrates so that it can jointly occupy the TD-BUS that is connected to it.

In the above, the arbitration device is configured to control each of the matching devices of the redundant structure so as to exchange status information of the matching device of the opposite side, and transfer the TD-BUS occupancy right according to the status change request signal applied from the control means in the matching device. After receiving, the partner matching device copies the data received through the 'SCC' communication path, stores the data in the DPRAM, and communicates with the peripheral processor through the TD-BUS.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

As can be seen in Figure 2 in the switching system according to the present invention, the peripheral processor and the device-to-device arbitration device is connected to a peripheral processor (10) connected to a higher processor (not shown), and through the peripheral processor 10 and the TD-BUS In the above-described conventional configuration consisting of a matching unit (20A) (20B) that is connected and configured in redundancy, and a plurality of devices (30A-30N) connected to the matching unit (20A) (20B) configured in redundancy and IPC The SCC communication path is connected to mutually communicate between the matching unit 20A and the matching unit 20B composed of the redundancy so as to exchange state information between the matching units 20A and 20B maintaining the active and standby states. And an arbiter 50 that arbitrates transmission and reception of control signals and data streams on a TD-BUS connecting the matching units 20A and 20B maintaining active and standby states with the peripheral processor 10. do.

As shown in FIG. 3, the matching units 20A and 20B configured as redundancy are operated in an active and standby mode, and communicate with the peripheral processor 10 through the TD-BUS. Device that is a data processing device by performing data transmission and reception and relaying of control signals between the peripheral processor 10 and the device 30A-30B which is a data processing device through communication with the device 30A-30N which is a data processing device through IPC. DPRAM that stores data and control signals transmitted and received between the 30A-30N and the peripheral processor 10 and outputs corresponding control signals and data streams according to access requests of the peripheral processor 10 or the device 30A-30N. Monitor and control the overall operation of the 21A and 21B and their matching units 20A and 20B, and monitor the memory capacity of the DPRAM 21A and 21B to detect a lack of memory capacity. To keep Is composed of control units 22A and 22B which perform general operations for utilizing DPRAM on the matching unit side.

In addition, the arbitration unit 50 is provided in each area so as to monitor the matching units 20A and 20B composed of redundancy, and the DPRAM memory area on the opposite side as requested by the control unit 22A and 22B. It is responsible for mediating so that it can be used.

In the above, the arbitration unit 50A and 50B transmit and receive the 'A_ST' signal and the 'B_ST' signal to each other to transmit / receive the state information of the other party and the state information of the other party to determine whether they are active or standby. Each of the matching units 20A and 20B included in the area is applied to the control unit 22A and 22B side, and the state signal of the other side is applied in accordance with ST_CHG, which is a state change request signal applied from the control unit 22A and 22B. After analyzing, the TD-BUS occupancy right with the peripheral processor 10 is transferred to the counterpart.

The operation of the arbitration unit 50A or 50B is performed by the clock CLK and the frame synchronization signal FS, the data transmission / reception completion signal / RDY, and lead-like information and address of data to be transmitted and received. It is executed according to the information (MOD / ADD0-3).

In the present invention including the functions described above, the mediation operation of the control signal and data stream between the peripheral processor and the device is as follows.

When the peripheral processor 10 intends to transmit a control signal or data to the lower level device 30A-30N, which is a data processing device, according to the control of the upper processor or an algorithm set to the first processor, the peripheral processor 10 is first connected to the TD-BUS. The state of the matching units 20A and 20B of the redundant structure is determined to recognize the matching unit 20A maintaining the active state, and then the corresponding control signal or data stream is kept active through the TD-BUS. The data is stored in the DPRAM 21A of the matching section 20A.

At this time, the control unit 22A in the matching unit 20A transmits the control signal or data stream stored in its DPRAM 21A through the IPC according to the timing shown in FIG. 4 to correspond to the corresponding device 30A-30N. The corresponding data processing is performed to the corresponding side, and the peripheral processor 10 connected to the TD-BUS is stored in the DPRAM 21A by storing the data processing result received through the IPC from the devices 30A-30N. Allows access to processing results.

Matching unit maintaining the active state while transmitting and receiving data and control signals between the peripheral processor 10 and the devices 30A-30N by the relay of the matching unit 20A maintaining the active state as described above. The control unit 22A in the 20A monitors the state of the DPRAM 21A on its own side and continuously monitors whether an abnormal state is entered due to an error in data processing, lack of a required buffer, or lack of memory capacity.

When it is determined that the monitoring information of the DPRAM 21A is abnormal, that is, when the memory pool is generated due to an excessive amount of data capacity to be processed, the controller 22A uses the counterpart matching unit 20B that maintains the standby state. The control signal 'ST_CHG' requesting the state change is applied to the arbitration unit 50A of its own in order to maintain the relay of the currently performed data.

The arbitration unit 50A receiving the 'ST_CHG' for the state change request transmits a signal 'A_ST' requesting confirmation of the status information to the arbitration unit 50B of the counterpart matching unit 20B, and then the arbitration unit 50B. In response to analyzing the response signal 'B_ST' received from the matching unit 20B, it is determined that the matching unit 20B can perform a normal operation, and transfers possession of the TD-BUS to the matching unit 20B.

At this time, the matching unit 20A maintaining the active state transmits its own data to the matching unit 20B side in the standby state through the 'SCC' communication path and maintains the standby state. The control unit 22B in the 20B copies it and stores it in the DPRAM 21B that it manages.

Therefore, the standby matching unit 20B, which has taken over the possession of the TD-BUS, receives the data from the active matching unit 20A through the 'SCC' communication path and copies and stores the data in the DPRAM 21B. The signal is relayed between the peripheral processor 10 and the device 30A-30N.

The above operation is performed repeatedly in software according to the amount of control signals and data processed between the peripheral processor 10 and the devices 30A-30N to efficiently use the matching units 20A and 20B composed of redundancy. do.

As described above, the present invention also provides a matching device that maintains a standby state according to the amount of control signals and data to be processed in a matching device having a redundant structure for relaying control signals and data between peripheral processors and lower-level devices in an exchange system. Used together, the system's load is shared, providing operational efficiency and rapid data processing.

Claims (2)

In the matching device of the redundant structure, A memory for storing data transmitted to and received from the processor; A control unit for monitoring the state information of the memory and notifying the matching device of the opposite side, and controlling the TD-BUS occupation right; And an arbitration unit for arbitrating data transmitted and received according to a control signal applied from the control unit. The method according to claim 1, The arbitration unit receives the occupancy rights of the TD-BUS according to the state change request signal applied from the control unit of the mating device, and copies and stores the data stored in the memory of the mating device into its own memory. Arbitration device of processor and device.