KR980013469A - Interprocessor communication device in all electronic exchanges - Google Patents

Abstract

The present invention relates to an inter-processor communication apparatus for performing a plurality of inter-processor communication in an electric electronic gantry, and more particularly, A first IPC control unit 61 for controlling the intervention of the maintenance channel M-BUS and the state of the node to which the processor is connected; a first IPC control unit 61 having a predetermined number of nodes to which the processor is connected, ) And outputs the status information signal including the state of the node and the functional state, and outputs a predetermined number of first interface units 62-D that share the M-BUS with the first IPC control unit 61 and the D- 69): a second IPC control unit (71) performing the same function as the first IPC control unit (61) and selectively active / standby by the redundancy signal; and a second IPC control unit Emitter is the same processor as the processor associated with the node of the face portions (62-69) is connected to a second interface portions (72-79) that perform the same function as the first interface portions (62-69).

The first and second IPC control units 61 and 71 and the plurality of interface units 62-69 and 72-79 are each formed of one board in order to facilitate maintenance, , Between the two IPC control units (61, 71)

The M-BUS, the D-BUS, the status information signal, and the redundant signal are interconnected by a flat cable. The IPC block is modularized in a board form, It is possible to maintain reliable inter-processor communication.

Description

Interprocessor communication device in all electronic exchanges

The present invention relates to an inter-processor communication device in an all-electronic exchanger, and more particularly, to an inter-processor communication (hereinafter referred to as " IPC ") device which provides communication channels between a plurality of processors, To an interprocessor communication device in an electronic interrupter capable of isolating faults when a fault occurs.

In general, the electronic repeater includes a plurality of Access Switching Subsystems (ASS) for performing distributed call processing functions and a Central Control Subsystem (CCS) for centralized operation and maintenance functions. And an Interconnection Network Subsystem (INS) for performing a centralized call processing function by connecting each connection switching subsystem or each connection switching subsystem and a central control subsystem.

Each subsystem includes a plurality of processors. Each of the sub-systems downloads an operating system and an application program in accordance with the characteristics thereof and performs a corresponding function of each processor, All electronic exchanges are operated.

Therefore, in order for the entire electronic exchanger to operate, mutual communication is required between a plurality of processors, and a plurality of inter-processor communication in the electronic exchanger is performed based on the IPC scheme as shown in FIG.

The IPC blocks 50 and 70 provide an IPC message communication channel to enable IPC message communication between the plurality of processors 10, 20, 30, 40 and 50 connected to the node, The processor monitors and controls various states for all connected nodes.

However, in the conventional IPC communication, depending on a subsystem in which a processor to be communicated is located, a central communication unit (CIPCU) or a center inter-processor communication unit (IIPCU) And the redundancy is implemented in one board, which makes it difficult to maintain the system, and it is also difficult to add a processor.

Accordingly, an object of the present invention is to provide an inter-processor communication device in an all-electronic exchanger that enables fault isolation and quick recovery in the event of a fault by duplicating and modularizing an IPC block that performs inter-processor communication in an all- .

An inter-processor communication device in an all-electronic exchanger according to the present invention is an apparatus for performing communication between a plurality of processors provided in an electric electronic device, comprising: a D- A first IPC control unit 61 for controlling the interworking of the BUS and the maintenance channel M-BUS and the state of the node to which the processor is connected; And outputs the status information signal including the state of the node and the functional state. The first IPC control unit 61 and the D-BUS include a predetermined number of first interface units (M- A second IPC control unit (71) which performs the same function as the first IPC control unit (61) and is selectively active / standby by the redundancy signal; and a second IPC control unit The second interface units 72-79 are connected to the same processor as the processor connected to the same processor as the processor connected to the nodes of the interface units 62-69 and perform the same function as the first interface units 62-69. .

The first and second IPC control units 61 and 71 and the interface units 52-69 and 72-79 are each formed of a single board for easy maintenance.

The M-BUS, D-BUS, status information signals, and duplicated signals between the first and second IPC control units 61 and 71 are connected to each other by a flat cable.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2 is a block diagram of an IPC apparatus according to the present invention. It is a block for transferring control messages and data for communication between distributed functional processors in a distributed electronic processor adopting a distributed processing structure. And a plurality of interface units 62-69 for performing interprocessor routing and interfacing between the redundancy IPC control units 61 and 71 and the plurality of processors connected to each node NODE.

In the TDX-100, there are eight duplicated interface units 62-69 and 72-79, and the interface units 62-69 and 72- 79), there are each node capable of connecting eight processors again.

Meanwhile, in order to stabilize the system, the IPC control unit 61 performs duplexing by selectively maintaining the active / standby state while exchanging duplicated signals with the duplicated IPC control unit 71. [

The IPC control unit 61 manages eight interfaces 62 to 69 to communicate with a plurality of processors (up to 63) connected to the nodes of the respective interface units 62 to 69 D-BUS is a path for data transmitted and received between processors, and is tri-stated for reliability.

In addition, M-BUS is a path for various control messages for maintaining IPC communication and is doubled for reliability.

The IPC control unit 71 for redundancy performs the same function as the IPC control unit 61. In the active state, the same processor as the plurality of processors connected to each node of the interface units 62-69 is connected to each node And manages inter-processor communication by managing the eight redundant interface units 72-79 connected thereto.

The duplicated IPC control units 61 and 71 monitor the status of the other party by exchanging status signals indicating their status, and control the control and redundancy of each node.

On the other hand, the duplicated IPC control units 61 and 71 control the redundancy by sharing signals relating to the functional Erry and Board hernion from the plurality of interfaces 52-69 and 72-79.

Particularly, for example, when one of the interface units 62 under the control of the IPC control unit 61 of the ping is disconnected or a self-function error occurs, the interface 72 is controlled by the redundant IPC control unit 71 And performs interprocessor communication instead.

On the other hand, even if an error occurs in one node of the interface 62-69, it is replaced with a corresponding node of the duplicated interface unit 72-79 to perform interprocessor communication.

In order to enable redundancy, the duplicated IPC control units 61 and 71 and the plurality of interface units 62-59 and 72-79 are implemented as a single board, and the D-BUS, M-BUS The boards share the function error and the herniation signal, and the dual IPC control units 61 and 71 share the same.

3, the IPC control unit 61 has a function of sharing the D-BUS to which the interface units 62 to 69 of the self are connected, BUS connected to the IPC controller 71 and the IPC controller 71 are respectively received and shared by the flat cable.

In contrast, the IPC control unit 61 and the redundancy IPC control unit 71 also share the D-BUS to which the interface units 72-79 of the self are connected and the interface unit 62 -69 and the IPC control unit 61 are connected to the D-BUS via a flat cable.

Meanwhile, the M-BUS is connected between the IPC control units 61 and 71 by a predetermined cable and shared among all the interface units 62-69 and 72-79.

The duplex signal and the status signal are connected by a flat cable between the IPC control units 61 and 71. The function error signal Fail and the hernia signal are transmitted from the interface units 52-69 and 72-79 to the IPC control unit 61 and 71 are connected to each other by a flat cable between the IPC control units 61 and 71 so that the IPC control units 61 and 71 can control the board herniation and function of the interface 62-69 and 72-79 of the other party, Error status can be monitored.

As described above, according to the present invention, since the redundancy of the IPC block performing the inter-processor communication in the entire electronic exchange is modularized into a board form, it is possible to isolate faults when a fault occurs, It is effective.

Figure 1 is a schematic block diagram of an IPC for interprocessor communication in a full-

Figure 2 is a block diagram of an IPC device according to the present invention;

DESCRIPTION OF THE REFERENCE NUMERALS

10, 20, 30, 40, 50: 1st, 2nd, 3rd, 4N processors 60, 70: IPC

61, 71: IPC control section 62-69, 72-79:

Claims (3)

An apparatus for performing communication between a plurality of processors provided in an electronic MFP, the apparatus comprising: a D-BUS as an interprocessor communication channel and an M-BUS as a maintenance channel based on a status information signal and a redundancy signal; A first IPC control unit 61 for controlling the state of a connected node; And a predetermined number of nodes to which the processor is connected to perform an interface with the processor and interprocessor routing, and outputs the state information signal including the state of the node and the state of the function And a predetermined number of first interface units (62-69) sharing the N-BUS with the first IPC control unit (61) and the D-BUS, A second IPC control unit 71 performing the same function as the first IPC control unit 61 and selectively active / standby by the redundancy signal; And a second interface unit 72-79 connected to the same processor as the processor connected to the nodes of the first interface units 62-69 and performing the same function as the first interface units 62-69, Interprocessor communication device in an electronic exchange. The IPC control unit according to claim 1, wherein the first and second IPC control units and the plurality of interface units are respectively configured as one board for easy maintenance, To-processor communication apparatus in an all-electronic exchanger. The method of claim 1 or 2, wherein the M-BUS, D-BUS, status information signals, and duplicated signals between the first and second IPC control units (61, 71) are interconnected by a flat cable Lt; RTI ID = 0.0 > exchanger. ≪ / RTI > ※ Note: It is disclosed by the contents of the first application.