JPH03245246A - Data transfer device - Google Patents

Abstract

PURPOSE:To improve the system performance by performing the transfer of data with the simultaneous control applied to both duplex buses and reducing temporarily the bus redundancy in order to attain the fast transfer of a large quantity of data. CONSTITUTION:A CPU 11 contained in a secondary control block 10 reads the data to be transferred out of a main storage part 12 and transfers them to a communication memory 13. Then a bus interface 14 is controlled and the data are transfered to a communication memory 4 via a 0-system bus 8. The data received by the memory 4 are transferred and stored into a main storage part 3 under the control of a CPU 2. That is, a 1-system bus 9 is normal but not used as shown in a diagram (a). In a diagram (b) both buses 8 and 9 are simultaneously controlled so that the fast communication is attained. If the bus 8, for example, has a fault, the normal communication is secured by the nondefective bus 9 as shown in a diagram (c). Meanwhile the communication is carried out by the bus 9 only owing to the fault of the bus 8 as shown in a diagram (d) even if the fast communication is tried via the block 10.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a data transfer device that mutually transfers data between a main control block and a sub-control block that are connected via a duplex bus and control a system. Regarding.

[Conventional technology]

Conventionally, in this type of data transfer device, control has been carried out to use only the regularly used bus out of the duplexed buses for regular use and backup, and the backup bus is switched over when the regular bus becomes a failure. I am using it.

[Problem to be solved by the invention]

As described above, conventional data transfer devices have the drawback that the duplexed buses are redundant because normally only one bus is used for data transfer, and the other bus cannot be used effectively.

An object of the present invention is to provide a data transfer device that can temporarily reduce bus redundancy, transfer a large amount of data at high speed, and improve system performance without causing problems in terms of failure resistance. It is in.

[Means to solve the problem]

The data transfer device of the present invention includes first and second buses provided between a main control block that controls the entire system and a sub-control block that controls each part of the system; a central control unit that controls a sub-control block; a first bus interface that corresponds to the first bus; one side is connected to the first bus interface and the other side is connected to the central control unit, and one side is connected to the central control unit to temporarily transmit and receive data; a first accumulating means for accumulating data, and a second bus interface corresponding to the second bus;
a second storage means, the other of which is connected to the central control unit, and which temporarily stores the transmitted and received data; and a third storage means, which stores the transmitted and received data under the control of the central control unit. Each of the main control block and the sub control block is provided with one of the first or second buses for normal communication, and for high-speed communication to confirm that the first and second buses are normal. ,
The device is configured to transfer data using the first and second buses simultaneously.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

Referring to FIG. 1 showing an embodiment of the present invention, a data transfer device includes a main control block 1 that controls the entire system, a sub control block 10 that controls each part in the system, and a main control block 1 and a sub control block 10 that control each part in the system. A 0-system bus 8 and a 1-system bus 9 are provided for communication with the control block 1-0. The main control block 1 has a central control unit 2 that controls the entire main control block 1, a bus interface 5 corresponding to the 0-system bus 8, and one side is connected to the bus interface 5 and the other side is connected to the central control unit 2 for transmission and reception. A communication memory 4 that temporarily stores data; a bus interface 7 that corresponds to the - system bus; and a communication device that temporarily stores transmitted and received data, with one side connected to the bus interface 7 and the other side connected to the central control unit 2. The sub control block 10 includes a memory 6 and a main memory section 3 that stores transmitted and received data under the control of the central control # section 2. The sub control block 10 is connected to a central control section 11 that controls the entire sub control block 10, Corresponding bus interface 14
, one side is connected to the bus interface 14, the other side is connected to the central control unit 11, and the communication memory 13 for temporarily storing transmitted and received data, the bus interface 16 corresponding to the 1-system bus, and the other side is connected to the bus interface 16 and the other side is The communication memory 15 is connected to the central control unit 11 and temporarily stores transmitted and received data, and the main storage unit 12 stores transmitted and received data under the control of the central control unit 11.

Note that FIG. 1 shows only the constituent elements necessary for realizing the present invention. Although the configurations within the main control block 1 and the sub-control block 10 are similar, they do not necessarily represent the same thing, but may have similar functions.

FIG. 2 is a diagram showing a control method for normal communication and high-speed communication in FIG. 1. The operation of transferring data from the sub control block 10 to the main control block 1 will be described below with reference to FIGS. 1 and 2. The central control units 1, 1 in the sub-control block 10 read the data to be transferred from the main storage unit 12 and transfer it to the communication memory 13. Thereafter, the data is transferred to the main control block 1 via the O-system bus 8 by controlling the bus interface 14 . Then, within the main control block 1, data is transferred to the communication memory 4 via the bus interface 5, and the received data on the communication memory 4 is transferred and stored in the main storage section 3 under the control of the central control section 2. Figure 2(a)
This is shown here. In FIG. 2(a), the 1-system bus 9 is shown in a normal but unused state. next,
In order to perform high-speed, single-speed communication, both the 0-system bus 8 and 1-system bus 9 are controlled simultaneously, and data is transferred simultaneously using both buses as shown in Figure 2(b). Communication becomes possible. The data transfer procedure on the 1-system bus 9 is also the same as that for the 0-system bus 8 described above.

When one bus fails, for example, the 0 system fails, the system shown in Figure 2 (
c) and (d). In FIG. 2C, normal communication is performed using the 1-system bus 9 since the 0-system bus 8 is unable to communicate due to a failure. On the other hand, even if the sub-control block 10 tries to perform high-speed communication, the 0-system bus 8 has failed and communication is performed only on the 1-system bus 9, resulting in the situation shown in FIG. The amount is the same as in FIG. 2(c).

Above, we have explained the case of a system with a bus with a redundant configuration, but a similar control method can be considered for a system with a bus with a triplex or higher configuration, making it possible to further speed up data transfer. .

〔Effect of the invention〕

As explained above, the present invention is capable of temporarily reducing bus redundancy and transferring a large amount of data at high speed by controlling both duplicated buses simultaneously and transferring data. There is no problem with respect to failure resistance, and system performance can be improved.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram showing one embodiment of the present invention, and FIG.
It is a figure which shows the control method of normal communication and high-speed communication in a figure. 1... Main control block, 2, 11...
Central control unit, 3, 12...Main storage unit, 4, 6,
13.15... Communication memory, 5, 7, 14.1
6...Bus interface, 8...-0
System bus, 9...1 system bus, 10...Sub control block.

Claims (1)

[Claims] first and second buses provided between a main control block that controls the entire system and a sub-control block that controls each part of the system; and a central control that controls the main control block or the sub-control block. a first bus interface corresponding to the first bus; and a first storage, one of which is connected to the first bus interface and the other of which is connected to the central control unit and which temporarily stores transmitted and received data. means, a second bus interface corresponding to the second bus, and a second storage, one of which is connected to the second bus interface and the other of which is connected to the central control unit, for temporarily storing transmitted and received data. and third storage means for storing the transmitted and received data under the control of the central control unit, respectively, provided in the main control block and the sub control block, and during normal communication, one of the first or second buses. 1. A data transfer device characterized in that during high-speed communication, the first and second buses are confirmed to be normal, and data is transferred using the first and second buses simultaneously.