JPH07248994A - Interface device - Google Patents

Abstract

PURPOSE:To effectively use a data bus of the limited width by switching the functional allocations of input and output buses of an extension module connected to an internal bus according to the operating state of the extension module. CONSTITUTION:An external I/F module 105 outputs a data bus connection request by a bus switch control signal 112 when a main body device 100 is started. A CPU 101 detects the bus connection request via an I/O port 104 and controls a bus switch module 106 by a bus switch control signal 113 to perform the proper connection of a data bus. That is, all data buses 111 of the module 105 are connected to a CPU data bus 108. A higher rank byte of the bus 111 of the module 105 is connected to a lower rank byte of the bus 108, and a lower rank byte of the bus 111 is connected to a lower rank byte of a DMA data bus 110 respectively. Then all buses 111 of the module 105 are used as the buses 110.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interface device for a computer system or its peripheral equipment.

[0002]

2. Description of the Related Art Conventionally, in an peripheral device such as a computer or a printer, an external interface (I / I
As a means for adding F), it is possible to provide an expansion slot into which the sub-board can be inserted and installed in the main body of the device, and to install a sub-board (external I / F module) on which an external I / F circuit is mounted in this slot It is generally done.

Generally, the main body has a plurality of expansion slots, and a plurality of external I / F modules can be mounted therein. In this type of device, access to the external I / F module is performed by the CPU data bus or the DMA data bus, and when the data transfer amount is not so large, such as input / output of control information of the external I / F module, or ,
If CPU program transfer is required, access via the CPU data bus. In addition, when high-speed and large-capacity data transfer is required, DMA is performed via the DMA data bus.
Input and output.

By thus selecting the bus according to the purpose of transfer, high-speed transfer of large-capacity data is performed without affecting the processing of the CPU. The DMA data bus width is the DMA bus width of the external I / F module,
It matches the data bus width of the DMA buffer. External I
When the data transfer with the / F module is a DMA transfer, the external I / F module issues a DMA request to the DMA controller to start the transfer. This transfer is performed between the DMA buffer and the external I / F module. At the end of the transfer, the CPU polls the status of the external I / F module or the external I / F module or DMA controller interrupts the CPU. And notify you.

[0005]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention
The bus width of the data bus generally matches the data bus width of the DMA buffer, but the desired bus width of the external I / F module depends on the contents of the I / F. this is,
It is determined by the I / F control chip mounted on the external I / F module.

If the control chip has a data bus width of 8 bits and the DMA data bus width is 16 bits,
The remaining 8 bits are unused. Therefore, in order to use the bus width without waste, it is necessary to convert 8 bits to 16 bits inside the external I / F module. In order to correspond to various functions of such an external I / F module, it is necessary to prepare a maximum bus width for the connection, which causes waste in the bus construction and increases the cost of the device. There is a problem that the mounting becomes large.

The present invention has been made in view of the above problems, and an object of the present invention is to provide an interface device capable of efficiently using a data bus having a limited bus width in connection with an external interface. Is to provide.

[0008]

In order to achieve the above object, the invention according to claim 1 connects a plurality of kinds of internal buses for transmitting a plurality of different data and an expansion module to the interface device. In an interface device having an input / output bus of a predetermined data width for
Means for detecting a connection request from the expansion module,
It comprises means for determining allocation of the input / output bus for the connection request, and means for switching the input / output bus according to the allocation to connect the plurality of types of internal buses to the input / output bus.

With the above structure, an efficient data bus interface environment is provided.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings. [First Embodiment] FIG. 1 is a block diagram showing the arrangement of an interface apparatus according to the first embodiment of the present invention. In the figure, reference numeral 100 is the interface device (hereinafter,
A main body, referred to as a device) 101 is a central control unit (CPU), 1
02 is a DMA controller, 103 is a DMA buffer,
Reference numeral 105 is an external I / F module. Further, 107 is an address bus, 108 is a CPU data bus, 109 is a read / write control signal, 110 is a DMA data bus, 1
Reference numerals 14 and 115 are DMA control signals.

The external I / F module 105 includes a main unit 100, an address bus 107, and a CPU data bus 10.
8, a read / write control signal 109, a DMA data bus 110, a DMA control signal 115, etc. External I
Access to the / F module 105 is performed via the CPU data bus 108 or the DMA data bus 110.

The device according to the present embodiment further includes an external I / O
A bus switch module 106 for switching the connection of the I / O port 104 for inputting and outputting information for performing bus configuration request and control of the F module 105, the CPU data bus 108, and the DMA data bus 110, and a bus switch control signal 112, It has 113. The external I / F module 105 issues a data bus connection request by the bus switch control signal 112 when the main body device 100 is started up.
The CPU 101 detects the request via the I / O port 104, controls the bus switch module 106 with the bus switch control signal 113, and makes an appropriate data bus connection.

FIG. 2 is a diagram showing an example of data bus connection. In the example shown in FIG. 2, the CPU data bus 10
8, DMA data bus 110, external I / F module 1
It is assumed that the data buses of 05 both have a 16-bit configuration. Generally, the bus width of the data bus is 1 Byte = 8 bi
It may be switched in units of t. Then, there are three combinations of (a), (b), and (c) in FIG.
In FIG. 2, 108U is the upper byte of the CPU data bus, 108L is the lower byte of the CPU data bus, 1
09U is the upper byte of the DMA data bus, and 1
09L indicates the lower byte of the DMA data bus. 111U is the upper byte of the data bus of the external I / F module, and 111L is the lower byte of the data bus of the external I / F module.

FIG. 2A shows a case where all the data buses 111 of the external I / F module are connected to the CPU data bus. Further, in (b), the upper byte 111U of the data bus of the external I / F module is connected to the lower byte 108L of the CPU data bus, and the lower byte 111L of the data bus of the external I / F module is the lower byte of the DMA data bus. The case where the byte 110L is connected is shown. In this case, the CPU data bus 108 and the DMA data bus 1
In the case of 10 as well, when accessing with 8 bits, the lower byte is used. Then, FIG. 2C shows the case where all the data buses 111 of the external I / F module are used as the DMA data buses.

As described above, the upper byte 111U of the data bus of the external I / F module is 108U, 108L,
110U, and the lower byte 111L of the data bus of the external I / F module is 108L, 110L.
Will be connected to either L. So CPU
When the 101 performs 8-bit access, if the upper byte 108U of the CPU data bus is used, the external I / O
The data bus 111 of the F module is divided into a CPU data bus 8 bit and a DMA data bus 8 bit, which are connected as shown in FIG. Therefore, the upper byte 111U of the data bus of the external I / F module is 108
It will be connected to either U or 110L.

In FIG. 3, as described above, the upper byte 111U of the data bus of the external I / F module is 108U,
An example of a circuit when connected to either 108L or 110U is shown. In the figure, reference numeral 301 denotes a decoding circuit for a bus switch control signal, which is an external I / F module 105.
Any of the signal lines 302 shown in the figure is asserted at the time of reading from, and any of the signal lines 303 of the figure is asserted at the time of writing. These signal lines are generated by decoding the bus switch control signal 113 and the read / write control signal 109.

At the time of DMA data transfer, the DMA controller 102 performs appropriate word width conversion control according to the data bus width of the external I / F module 105 and the bus width of the DMA data buffer 103. This is performed by the CPU 101 setting the operation mode for the DMA controller 102 prior to the DMA data transfer. For example,
When the data width of the DMA data bus 110 is 16 bits and the DMA data bus width of the data bus 111 of the external I / F module 105 is 8 bits, the data is once held in an internal register (not shown) of the DMA controller 102, 8/16 bit conversion or DM
This conversion function is added to the A buffer 103.

As described above, according to this embodiment,
A bus switch module for changing the connection of the data bus is provided between the data bus of the external I / F module, and the DMA data bus and the CPU data bus, and the DMA data bus width and the CPU data are set within a fixed data bus width. By switching the bus width allocation, it is possible to use the data bus efficiently.

In the first embodiment, the bus switch module 106 is set when the main unit 100 is started up. However, the bus switch module 106 may be changed according to the operating state of the external I / F module 105. Good. For example,
16 when accessing the CPU
Bits are assigned, and DM is used for high-speed data transfer.
The A data bus 16 bits may be allocated. [Second Embodiment] FIG. 4 is a block diagram showing the arrangement of an interface apparatus according to the second embodiment of the present invention. In the device shown in FIG. 4, the same components as those of the device according to the first embodiment shown in FIG. 1 are designated by the same reference numerals, and the description thereof will be omitted here.

In the apparatus according to this embodiment, the external I / F module 105 directly controls the bus switch module 106 with the bus switch control signal 401. in this case,
The CPU 101 detects the DMA data bus width from the bus switch module, and sets the bus width when performing the DMA transfer according to the DMA controller 102 or the DMA buffer 103.

The bus switch control information is the first
Similar to the embodiment described above, an I / O port may be provided for detection, or the transfer bus width may be controlled by directly connecting to the DMA controller 102. The DMA data bus width is
Similar to the first embodiment, it may be changed according to the operating state of the external I / F module 105. In this case, when changing the bus width, the external I / F module 105 may generate an interrupt to the CPU 101 and notify it. CP
The U 101 correspondingly changes the DMA operation and the access to the external I / F module 105.

The present invention may be applied to a system composed of a plurality of devices or an apparatus composed of a single device. Further, it goes without saying that the present invention can be applied to the case where it is achieved by supplying a program to a system or an apparatus.

[0023]

As described above, according to the first aspect of the invention, the functional allocation of the input / output bus of the expansion module connected to the internal bus is switched according to the operating state of the expansion module. As a result, the data bus having the limited data width can be efficiently used.

According to the second aspect of the present invention, the input / output buses are assigned in units of predetermined bytes so as to match the bus configuration of the internal bus, so that the input / output buses can be switched smoothly. .

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an interface device according to a first exemplary embodiment of the present invention.

FIG. 2 is a diagram showing a connection example of a bus switch module.

FIG. 3 is a block diagram showing a circuit example of a bus switch module.

FIG. 4 is a block diagram showing a configuration of an interface device according to a second exemplary embodiment of the present invention.

[Explanation of symbols]

 100 Interface Device Main Body 101 CPU 103 DMA Buffer 104 I / F Port 105 External I / F Module 106 Bus Switch Module 301 Bus Switch Control Signal Decoding Circuit

Claims (4)

[Claims] 1. An interface device having a plurality of types of internal buses for transmitting a plurality of different data and an input / output bus of a predetermined data width for connecting an expansion module to the interface device, wherein the connection from the expansion module is provided. Means for detecting a request; means for determining allocation of the input / output bus to the connection request; means for switching the input / output bus according to the allocation to connect the plurality of types of internal buses to the input / output bus An interface device comprising: 2. The interface device according to claim 1, wherein the assignment of the input / output bus is performed in a predetermined byte unit so as to match the bus configurations of the plurality of types of internal buses. 3. The interface device according to claim 1, wherein the assignment of the input / output bus can be changed according to the function of the expansion module. 4. The expansion module directly controls switching of the input / output bus.
The interface device according to.