JPH07182270A - Address/data multiplex-controllable rom internal circuit - Google Patents

Abstract

PURPOSE:To provide a ROM internal circuit capable of easily increasing the number of terminals to be used for outputting data from a ROM without increasing the number of terminals in a conventional ROM package in respect to data width longer than the bit width of a data bus for a ROM. CONSTITUTION:The ROM internal circuit constituted of an address input terminal means 101, decoder means 102, 103, a memory cell array 104, an output buffer means 106, and a data output terminal means 107 has an address latch means 115 for latching an inputted address and transmitting the latched address to the means 102, 103, an address/data multiplex bus bidirectonal buffer means 114 for transmitting an address from the means 101 to the means 115 at the time of inputting the address and transmitting a prescribed bit in data to the means 101 at the time of outputting the data and a bus for connecting the means 106 to the means 114.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ROM internal structure, and more particularly, it enables data input / output with a data width larger than the bit width of a ROM data bus in a ROM internal circuit.
Relating to ROM internal circuit.

[0002]

2. Description of the Related Art FIG. 4 is a block diagram showing a configuration of a conventional ROM internal circuit example.
Decoder 402, Y decoder 403, memory cell array 404, Y gate circuit 405, output buffer 4
06, a data terminal 407, and a CE circuit 4 that receives a chip enable (hereinafter, referred to as CE) signal 411.
08, an OE circuit 409 that receives an output enable (hereinafter, referred to as OE) signal 412, and a P that receives a program (hereinafter, referred to as PRG) signal 413.
It is composed of an RG circuit 410.

The address externally input to the address terminal 401 is input to the X decoder 402 and the Y decoder 403 when the CE signal 411 is input to the CE circuit 408. Memory cell array 404 obtained by address decoding by X decoder 402 and Y decoder 403
When the OE signal 412 is input to the OE circuit 409, the data of the output of the output buffer 4 is output via the Y gate circuit 405.
The data is output from 06 to the data terminal 407. The address must be continuously input from the address terminal 401 during the read operation. The output data is output to the outside only from the data terminal 407.

FIG. 5 is a block diagram showing the configuration of a conventional ROM internal circuit example.

FIG. 5A shows an example in which two ROMs having a 16-bit width data bus are used and connected to a CPU having a 32-bit width data bus. In FIG. 5A, C
An address bus 504, a 32-bit wide data bus 505, and a control bus 506 are connected to each of the PU 501 and the ROMs 502 and 503. However, the data buses 507 and 508 connected from the data bus 505 to the ROMs 502 and 503 are the data buses 505.
Is divided into two and each has a 16-bit width. The control bus 506 is a bus for ROM select signals such as CE signals, OE signals, and PRG signals.

In FIG. 5A, a 32-bit word (hereinafter
When performing a read operation (described as a long word), the RO is read from the CPU 501 via the address bus 504.
Read access is made by inputting an address to M502 and 503. From the ROMs 502 and 503, 16-bit data is output to the data bus 505 corresponding to the input address. The CPU 501 is the ROM 50
32-bit data can be obtained from the data bus 505, with the data output from 2 as lower data (or upper data) and the data output from the ROM 503 as upper data (or lower data). Figure 6B
FIG. 5B is a time chart at the time of reading the ROM of FIG. 5A.

FIG. 5B shows one ROM having a 16-bit wide data bus and C having a 32-bit wide data bus.
This is an example of connecting to the PU and accessing twice. In FIG. 5B, the CPU 511 has an address bus 514, a 32-bit wide data bus 515, and a control bus 5.
16 are connected. Further, the control bus 516 is directly connected to the ROM 512, the address bus 514 and the control bus 516 are connected via the address latch circuit 517, and the data bus 515 is connected via the data latch circuit 518. The control bus 516 is a ROM select signal bus.

When performing a longword read operation in FIG. 5B, the address bus 5 is transferred from the CPU 511.
14 through the address latch circuit 517 and the ROM 5
Input the address to 12 and read access. The input address is latched by the address latch circuit 517 and input to the ROM 512. From the ROM 512, 16-bit data is output twice to the data latch circuit 518 corresponding to the input address. In the data latch circuit 518, the output data is latched twice for every 16 bits and sequentially allocated to the 32-bit data bus 515 for output. CPU511
Can obtain 32-bit data from the data bus 515. FIG. 6C is a time chart diagram when reading the ROM of FIG. 5B.

[0009]

In the conventional circuit configuration, in the case of FIG. 5A, the required ROM capacity is small, and
Even when only one ROM is required, two ROMs are used. Therefore, there are problems that the cost increases due to the increase in the number of ROMs used, the mounting area of the entire LSI increases, and the efficiency of maintenance is reduced when the ROM design is changed. Further, in the case of FIG. 5B, as shown in the time chart of FIG.
Since the read operation is executed once, the ROM access time is doubled.

In view of the above points, the present invention is a ROM
For a data width larger than the bit width of the data bus of
R without increasing the number of terminals of the conventional ROM package
An object of the present invention is to provide a ROM internal circuit capable of address / data multiplex control capable of easily increasing the number of terminals usable for data output of OM.

[0011]

A ROM internal circuit capable of address / data multiplex control according to the present invention addresses an address input terminal means for inputting an address from the outside and the address input from the address input terminal means. Decoder means for decoding, memory cell array, output buffer means for holding data output from the memory cell array corresponding to the address decoded by the decoder means, and the data output from the output buffer means Is a ROM internal circuit configured to output to the outside, latches the address input from the address input terminal means, and transmits the address to the decoder means.
Address latch means, and when the address is input from the outside, the address is transmitted from the address input terminal means to the address latch means, and when the data is output from the output buffer means, a predetermined bit of the data To the address input terminal means, and a data bus connecting the address / data multiplex bus bidirectional buffer means and the output buffer means to the address / data multiplex bus bidirectional buffer means.

In the address / data multiplex controllable ROM internal circuit of the present invention, the address latch means includes an address latch circuit and an address latch signal generation circuit, and the address latch signal generation circuit generates the address latch signal. The address latch signal is input to the address latch circuit, and the address latch signal is activated to latch the input address in the address latch circuit.

In the ROM internal circuit capable of address / data multiplex control according to the present invention, the address / data multiplex bus bidirectional buffer means comprises an address / data multiplex bus bidirectional buffer and an address / data multiplex bus. A plex bus direction control signal generation circuit, and the address data multiplex bus direction control signal generated in the address data multiplex bus direction control signal generation circuit
Input to bidirectional buffer for data multiplex bus,
By setting the address / data multiplex bus direction control signal to the standby state, the address / data multiplex bus bidirectional buffer is controlled to transmit an address from the address input terminal means to the address latch circuit. , By activating the address / data multiplex bus direction control signal,
The address / data multiplex bus bidirectional buffer is controlled to transfer data from the output buffer means to the address input terminal means.

In the ROM internal circuit capable of address / data multiplex control according to the present invention, the output buffer means has at least the total number of bits of the address input terminal means and the number of bits of the data output terminal means. Have.

In the ROM internal circuit capable of address / data multiplex control according to the present invention, the address input terminal means inputs an address from the outside and outputs the data to the outside.

[0016]

[Action]

a) When the address / data multiplex bus direction control signal is set to the standby state, the bidirectional buffer for the address / data multiplex bus is controlled to transmit the address from the address input terminal means to the address latch circuit section. To be done.

At this time, when an address is externally input to the address input terminal means, the address is supplied to the address latch circuit via the address / data multiplex bus bidirectional buffer. By setting the address latch signal to the active state, the address is latched in the address latch circuit, and the address is continuously supplied to the decoder means until the address latch signal is set to the active state next time.

B) When the address / data multiplex bus direction control signal is set to the active state, the bidirectional buffer for the address / data multiplex bus becomes
It is controlled to transfer data from the output buffer means to the address input terminal means.

At this time, the data of the memory cell array which has been address-decoded by the decoder means is output from the output buffer means to the address input terminal means through the data output terminal means and the address / data multiplex bus bidirectional buffer. To be done.

[0020]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a ROM internal circuit according to an embodiment of the present invention. FIG. 1 shows the configuration of the conventional ROM internal circuit shown in FIG. 4, in addition to the address terminal 401, the address / data multiplex terminal 101, the address / data multiplex bus bidirectional buffer 114, and the address. A latch circuit 115,
An address / data multiplex bus direction control signal generation (hereinafter referred to as DIR) circuit 116 and an address latch signal generation (hereinafter referred to as ALE) circuit 117 are included.

Address / data multiplex terminal 1
Reference numeral 01 inputs an address input from the outside to the address / data multiplex bus bidirectional buffer 114, and outputs the data output from the output buffer 106 to the outside. The address / data multiplex bus bidirectional buffer 114 is controlled by the address / data multiplex bus direction control signal 118 to transmit the address input from the address / data multiplex terminal 101 to the address latch circuit 115, or The data output from the output buffer 106 is transmitted to the address / data multiplex terminal 101. The address latch circuit 115 is controlled by the address latch signal 119 and latches the address. DIR circuit 11
6 generates an address / data multiplex bus direction control signal 118 which controls the bidirectional buffer 114 for the address / data multiplex bus. ALE circuit 1
17 generates an address latch signal 119 which controls the address latch circuit 115. Output buffer 106
Has a bit width obtained by combining the number of bits of the address / data multiplex terminal 101 and the number of bits of the data terminal 107.

When the ROM internal circuit is in the steady state, the address / data multiplex bus direction control signal 118 generated by the DIR circuit 116 is set to the standby state, and the bidirectional buffer 114 for the address / data multiplex bus is set. Is controlled to transmit an address from the address / data multiplex terminal 101 to the address latch circuit 115.

The read operation of the ROM in FIG. 1 will be described with reference to the time chart diagram of FIG. 3 for reading the ROM of the embodiment of the present invention. First, when an address is input, the address externally input to the address / data multiplex terminal 101 is input to the address latch circuit 115 when the CE signal 111 input to the CE circuit 108 is set to an active state. To be done. ALE circuit 11
When the address latch signal 119 input to the address latch circuit 115 from 7 is set to the active state, the address is latched by the address latch circuit 115 and input to the X decoder 102 and the Y decoder 103. This allows
After the address is latched in the address latch circuit 115, the address / data multiplex terminal 1
It is not necessary to continue inputting the address into 01.

Next, when outputting the data, the DIR
The address / data multiplex bus direction control signal 118 generated by the circuit 116 is set to an active state, and the bidirectional buffer 11 for the address / data multiplex bus is set.
4 is controlled in a state of transmitting data from the output buffer 106 to the address / data multiplex terminal 101 and the data terminal 107.

The data of the memory cell array 104 which has been address-decoded by the X decoder 102 and the Y decoder 103 is output to the output buffer via the Y gate circuit 105 when the OE signal 112 input to the OE circuit 109 is set to the active state. The data is output from the data terminal 106 to the address / data multiplex terminal 101 via the data terminal 107 and the address / data multiplex bus bidirectional buffer 114.

When the data output is completed and the CE signal 111 and the OE signal 112 are set to the standby state, the address / data multiplex bus direction control signal 118 is set to the standby state again, and the ROM internal circuit is in the steady state. Becomes

FIG. 2 is a block diagram showing the structure of a ROM access circuit according to an embodiment of the present invention. In FIG. 2, an address bus 204, a 32-bit width data bus 205, and a control bus 206 are connected to the CPU 201. Further, in the ROM 202, the data bus 205 is directly connected to the data terminal, the control bus 206 is directly connected to the ROM select signal, and the address / data multiplex bus control circuit 20 is further provided.
To the terminal for address / data multiplex via 7,
The address bus 204 and the data bus 205 are connected. The ROM 202 has the same circuit configuration as the ROM internal circuit of FIG. The control bus 206 is a ROM
This is a select signal bus.

When performing a longword read operation in FIG. 2, the address / data multiplex bus control circuit 207 is arranged from the address bus 204 to the ROM 20.
It controls to input the address to 2. CPU201
When a read access is made by inputting an address from the address, the address is input to the ROM 202 via the address / data multiplex bus control circuit 207. Next, the address / data multiplex bus control circuit 207 is set to R
The OM 202 is controlled to output data to the data bus 205. The data corresponding to the address input to the ROM 202 is output to the data bus 205 directly from the data terminal of the ROM 202 and from the address / data multiplex terminal via the address / data multiplex bus control circuit 207. FIG. 6A is a time chart when the ROM of FIG. 2 is read.

[0030]

As described above, according to the present invention, the conventional ROM internal circuit latches the address inputted from the outside and supplies the address internally, and the address latch circuit from the address terminal. By adding a bidirectional buffer for transmitting an address to the memory and transmitting data from the output buffer to the address terminal, the address terminal can also be used as a data terminal, and the bit of the ROM data bus can be used. When reading a data width larger than the width, it is possible to easily increase the number of terminals that can be used as the data output terminals of the ROM without increasing the number of terminals of the conventional ROM package.

Therefore, compared with the conventional access method using two ROM internal circuits, the number of ROMs used is reduced to reduce the cost, reduce the mounting area of the entire LSI, and design the ROM. It has the effect of facilitating maintenance efficiency when changes occur. Also,
Compared with the conventional access method of accessing the ROM internal circuit twice, by performing one data output by one read operation, the ROM access time can be shortened.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a ROM internal circuit according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a ROM access circuit according to an embodiment of the present invention.

FIG. 3 is a time chart diagram when reading a ROM according to an embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration of a conventional ROM internal circuit example.

FIG. 5 is a block diagram showing a configuration of a conventional ROM access circuit example.

FIG. 6 is a time chart comparison diagram when reading a ROM according to an embodiment of the present invention and a conventional example.

[Explanation of symbols]

101 address / data multiplex terminal 401 address terminal 102, 402 X decoder 103, 403 Y decoder 104, 404 memory cell array 105, 405 Y gate circuit 106, 406 output buffer 107, 407 data terminal 108, 408 chip enable circuit 109, 409 Output enable circuit 110, 410 Program circuit 111, 411 Chip enable signal 112, 412 Output enable signal 113, 413 Program signal 114 Address / data multiplex bus bidirectional buffer 115 Address latch circuit 116 Address / data multi Plex bus direction control signal generation circuit 117 Address latch signal generation circuit 118 Address / data multiplex bus direction control Signal 119 Address latch signal 201, 501, 511 CPU 202, 502, 503, 512 ROM 204, 504, 514 Address bus 205, 505, 515 Data bus (32 bits) 206, 506, 516 Control bus 207 Address / data multiplex Bus control circuit 507, 508 Data bus (16 bits) 517 Address latch circuit 518 Data latch circuit

Claims (5)

[Claims] 1. An address input terminal means for inputting an address from the outside, a decoder means for address decoding the address input from the address input terminal means, a memory cell array, and the address decoded by the decoder means. In the ROM internal circuit, which is composed of output buffer means for holding the data output from the memory cell array corresponding to, and data output terminal means for outputting the data output from the output buffer means to the outside, Address latch means for latching the address inputted from the address input terminal means and transmitting it to the decoder means; and, when the address is inputted from the outside, from the address input terminal means to the address latch means. The address is transmitted and the Is output from the output buffer means, a bidirectional buffer means for address / data multiplex bus for transmitting a predetermined bit of the data to the address input terminal means, the output buffer means and the address / data multiplex. A ROM internal circuit capable of address / data multiplex control, comprising: a data bus connecting to the bus bidirectional buffer means. 2. The address latch means has an address latch circuit and an address latch signal generation circuit, and inputs the address latch signal generated in the address latch signal generation circuit to the address latch circuit,
By activating the address latch signal,
2. The ROM internal circuit capable of address / data multiplex control according to claim 1, wherein the address latch circuit latches an input address. 3. The address / data multiplex bus bidirectional buffer means includes an address / data multiplex bus bidirectional buffer and an address / data multiplex bus direction control signal generation circuit, Input the address / data multiplex bus direction control signal generated in the data multiplex bus direction control signal generation circuit to the address / data multiplex bus bidirectional buffer and wait for the address / data multiplex bus direction control signal. By setting the state, the bidirectional buffer for address / data multiplex bus is controlled to the state of transmitting an address from the address input terminal means to the address latch circuit, and the address / data multiplex bus direction control signal is transmitted. In an active state 2. The address / data multiplex control according to claim 1, wherein the bidirectional buffer for the address / data multiplex bus is controlled to transfer data from the output buffer means to the address input terminal means. Possible ROM internal circuit. 4. The address / data multiplex control according to claim 1, wherein the output buffer means has a bit number that is a combination of at least the bit number of the address input terminal means and the bit number of the data output terminal means. Possible ROM internal circuit. 5. An address / data multiplex controllable ROM internal circuit according to claim 1, wherein said address input terminal means inputs an address from the outside and outputs data to the outside.