JPH11282590A - Plural system bus control microcomputer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent influence of the potential fluctuation to an outside element whose access frequency is high on an outside element whose access frequency is low, to prevent the increase of current consumption, and to prevent the influence of spurious radiating noise to the outside element whose access frequency is low. SOLUTION: In this bus control microcomputer, two system outside buses 14 and 15 are connected with two sets of ports 12 and 13, and a flash memory 3 whose access frequency from a microcomputer 11 is high is connected with the outside bus 14, and an SRAM(static RAM) 4 and a G/A(gate array) 5 whose access frequency from the microcomputer 11 is low are connected with the outside bus 15. Moreover, access is performed only to one outside bus among the two system outside buses 14 and 15 according to a chip select signal, and even when the potential of a data bus 18 whose access frequency is high fluctuates, any influence on a data bus 22 whose access frequency is low can be prevented, and the increase of current consumption can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-system bus control microcomputer for inputting and outputting data to and from a plurality of external elements.

[0002]

2. Description of the Related Art FIG. 6 is a block diagram showing a conventional external bus control microcomputer.
Is a microcomputer (hereinafter referred to as a microcomputer), 2
Is a port dedicated to connecting external elements provided in the microcomputer 1,
A flash memory 3 is provided outside the microcomputer 1 and stores a processing program or the like with a high access frequency. A static RAM (hereinafter referred to as an SRAM) is provided outside the microcomputer 1 and temporarily stores data with a low access frequency. 5) is a gate array (hereinafter referred to as G / A) which is provided outside the microcomputer 1 and controls external devices and the like by a logic circuit.
). Reference numerals 6 to 10 denote external buses for connecting the port 2 to the flash memory 3, SRAM 4 and G / A 5, 6 to 8 address buses, 9 a control bus, and 10 a data bus.

Next, the operation will be described. In the conventional microcomputer 1, the processing program is stored in an externally connected flash memory 3 or the like in response to a case where the processing program cannot be stored only by the capacity of the built-in ROM. Generally, the processing program is read via an external bus. In FIG. 6, the microcomputer 1, the flash memory 3, and the SRAM 4
When writing data to or reading data from the G / A 5, the microcomputer 1 uses the port 2
A control signal is output to the flash memory 3, SRAM 4 or G / A 5 to be accessed via the control bus 9, and an address is specified via the address buses 6 to 8. Read and write data.

[0004]

Since the conventional external bus control microcomputer is configured as described above, the connection between the microcomputer 1 and the flash memory 3, the SRAM 4, and the G / A 5 is provided in the microcomputer 1. This configuration is made up of a set of ports 2 dedicated to external device connection and a single external bus connected to the port 2. Therefore,
A flash memory 3 in which a processing program with a high access frequency is stored, an SRAM 4 for temporarily storing data with a low access frequency, and a G / A 5 for controlling external devices and the like.
Is connected as an external element, data is input to and output from the data bus 10 every time the flash memory 3 having a high access frequency is accessed. Of the SRAM 4 and the connection terminal of the G / A 5 having a low power consumption, and the current consumption is increased in the input protection circuit provided at the terminal. Further, unnecessary radiation noise is generated due to the fluctuation of the potential of the data bus 10, but there is a problem that the unnecessary radiation noise also affects the SRAM 4 and the G / A 5.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and it is possible to prevent a potential change of an external element having a high access frequency from affecting an external element having a low access frequency, thereby preventing an increase in current consumption. It is another object of the present invention to provide a microcomputer for controlling a plurality of bus systems, which prevents unnecessary radiation noise from affecting an external device having a low access frequency.

[0006]

According to the present invention, there is provided a multi-system bus control microcomputer according to the present invention, which comprises a microcomputer having m sets of external element connection terminals and a frequency of accessing the n external elements by the microcomputer. m sets of external element connection terminals and n external elements
An external bus that is connected to the external bus in a different manner, the microcomputer selects one of the m external buses and inputs or outputs data to or from an external element connected to the external bus. , And other data buses.

A microcomputer for controlling a plurality of buses according to the present invention includes a microcomputer having two sets of external element connection terminals and a microcomputer having two sets of external element connection according to the frequency of access to the plurality of external elements by the microcomputer. The microcomputer includes an external bus in which terminals and a plurality of external elements are classified into two systems and connected.
One of the external buses is selected to input or output data with an external device connected to the external bus, and the data bus of the other system is shut off.

In the microcomputer for controlling multiple buses according to the present invention, the microcomputer is provided with an address data fixing unit for fixing the address data of the address bus of the other system.

A multi-system bus control microcomputer according to the present invention includes a microcomputer having two sets of external element connection terminals respectively connected to two internal buses, and a microcomputer which controls access frequency of a plurality of external elements by the microcomputer. Accordingly, the microcomputer includes an external bus in which two sets of external element connection terminals and a plurality of external elements are classified and connected to two systems, and the microcomputer connects one of the two systems, the internal bus and the external bus. It selects and inputs or outputs data with an external element connected to the external bus.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below. Embodiment 1 FIG. FIG. 1 is a block diagram showing a multi-system bus control microcomputer according to a first embodiment of the present invention. In FIG. 1, reference numeral 3 denotes a microcomputer provided outside a microcomputer (hereinafter, referred to as a microcomputer) 11, which has a high access frequency. A flash memory (external element) 4 in which a processing program and the like are stored is provided outside the microcomputer 11, and a static RAM (hereinafter referred to as an SRAM: external element) for temporarily storing data with low access frequency, and 5 is a microcomputer 11 And a gate array (hereinafter, referred to as G / A: external element) that controls an external device or the like by a logic circuit. As described above, the configuration is the same as that of the related art shown in FIG.

In the microcomputer 11, reference numerals 12 and 13 denote ports (terminals for connecting external elements). Reference numeral 14 denotes an external bus connecting the port 12 and the flash memory 3;
Reference numeral 5 denotes an external bus for connecting the port 13 to the SRAM 4 and the G / A 5. The external bus 5 is classified into two systems, such as the flash memory 3 frequently accessed by the microcomputer 11 and the SRAM 4 and G / A 5 with low access frequency. External buses 14 and 15 are connected. In the external bus 14, 16 is an address bus, 17 is a control bus,
18 is a data bus. Further, in the external bus 15, 19 and 20 are address buses, 21 is a control bus, 22
Is a data bus.

FIG. 2 is a conceptual diagram showing the internal configuration of the microcomputer. In FIG.
U and 32 are ROM, 33 is RAM, 34 is peripheral function, 3
Reference numeral 5 denotes a port. The port 35 includes the ports 12 and 13 shown in FIG. 36 is an internal bus. The internal bus 36 of the microcomputer 11 according to the first embodiment is constituted by one system. FIG. 3 is a block diagram showing an external bus extension function of the microcomputer. In FIG.
2 is a function selection terminal.

Next, the operation will be described. As shown in FIG. 2, the microcomputer 11 performs processing by the CPU 31 according to a processing program stored in the ROM 32 and
Control. However, the microcomputer 11 stores the processing program in the externally connected flash memory 3 or the like and stores the processing program through the port 35 and the external bus 14 in response to the case where the processing program cannot be stored only by the capacity of the built-in ROM 32. Generally, the processing program is read out. FIG. 3 shows a configuration used when expanding the two-system external buses 14 and 15 as shown in FIG. 1, and as shown in FIG.
1 writes a preset value to the mode register 41 via the internal bus 36, thereby the two external buses 1
4 and 15 or as shown in FIG.
U31 expands the two external buses 14 and 15 by supplying a preset potential to the function selection terminal 42 via the internal bus 36. This extension allows port 3
A part of 5 can be used as ports 12 and 13 for connecting external elements as shown in FIG.

Next, in FIG. 1, the microcomputer 11
Ports 12 and 13 and control buses 17 and 2 from PU 31
1 and the flash memory 3 and the SRAM 4, G /
A5. A chip select signal is output to A5, and in response to the access of the chip select signal, two external buses 14, 1
5 is selected to input or output data with an external element connected to the external bus. For example, when the external bus 14 is selected by a chip select signal and a processing program stored in the flash memory 3 is read, an address is specified from the microcomputer 11 via the port 12 and the address bus 16,
By activating the read signal (RD signal), the processing program at the designated address can be read via the data bus 18. At this time, by not outputting a chip select signal to the external bus 15 and setting the data bus 22 of the external bus 15 to a floating state (blocking), the processing program input from the external bus 14 and the external bus 15 Is the microcomputer 1
1 to prevent collision. Also, for example,
The external bus 15 is selected by the chip select signal,
When writing data to the AM 4, an address is designated from the microcomputer 11 via the port 13 and the address bus 20, and the data is written to the designated address by activating the write signal (WR signal) on the control bus 21. Writing can be performed via the data bus 22. At this time, no chip select signal is output to the external bus 14, and the data bus 18 of the external bus 14
By not outputting data to the flash memory 3 (blocking), writing of data to the flash memory 3 is prevented.

In the first embodiment, two sets of ports for connecting external elements are provided, and two sets of external buses 14 and 15 are connected to the two sets of ports, and the two sets of external buses 14 and 15 are connected. A plurality of external elements according to the frequency of access by the microcomputer 11 are classified and connected, but three or more sets of ports for connecting external elements are provided, and three or more external buses are connected to the three or more sets of ports. Alternatively, a plurality of external elements may be classified and connected to the three or more external buses according to the access frequency of the microcomputer 11.

As described above, according to the first embodiment, two sets of external buses 14 and
15, the external bus 14 is connected to the flash memory 3 frequently accessed by the microcomputer 11, and the external bus 15 is connected to the SRAM 4 and the G / A 5 that are not frequently accessed by the microcomputer 11, and further to a chip select. Since only one of the two external buses 14 and 15 is accessed by the signal, the flash memory 3 which is frequently accessed is accessed to input / output data to / from the data bus 18 and the data is input / output. Even if the potential of the bus 18 fluctuates, S
This does not affect the data bus 22 of the RAM 4 and the G / A 5, thereby preventing an increase in current consumption. Further, it is possible to prevent the unnecessary radiation noise from affecting the SRAM 4 and the G / A 5 due to the potential fluctuation of the data bus 18.

Embodiment 2 FIG. FIG. 4 is a block diagram showing a multi-system bus control microcomputer according to a second embodiment of the present invention. In the figure, reference numerals 51 and 53 output address data in the microcomputer 11 to an address bus as it is in response to a chip select signal. Bus latch circuits (address data fixing units) for latching address data and outputting fixed address data to an address bus, and 52 and 54 are address bus ports included in the ports 12 and 13. The other reference numerals are the same as those in the first embodiment, and the description thereof will not be repeated.

Next, the operation will be described. In the first embodiment, the data bus on the inactive side of the chip select signal is cut off in order to prevent data collision and write error due to the data on the inactive side of the chip select signal. Although there is little change, addresses are output from both systems for the address bus. Therefore, in the first embodiment, bus latch circuits 51 and 53 are provided between the internal bus 36 in the microcomputer 11 and the address bus ports 52 and 54 of both systems, and when the chip select signal becomes active, The address data latched by the bus latch circuit of the system is released, and the address data is output from the microcomputer 11 to an external element. When the chip select signal becomes inactive, the address data of that system is latched by a bus latch circuit to fix the address data.

As described above, according to the second embodiment, when the chip select signal becomes inactive,
The address data of the system is transferred to the bus latch circuits 51 and 53.
, And the address data is fixed, so that even if the potentials of the address buses 16, 19, and 20 fluctuate, they do not affect the address buses of other systems and prevent an increase in current consumption. can do. Also,
It is possible to prevent unwanted radiation noise from affecting other systems due to potential fluctuations of the address buses 16, 19, and 20.

Embodiment 3 FIG. 5 is a conceptual diagram showing the internal configuration of a microcomputer according to Embodiment 3 of the present invention. In FIG. 5, reference numerals 36 and 61 denote two internal buses consisting of a control bus, a data bus and an address bus.
The internal buses 36 and 61 of the system are connected to the external buses 15 and 14 via the ports 13 and 12. Also, 62
Is a bus interface unit (BIU) for controlling the two internal buses 36 and 61. The other reference numerals are the same as those in the first embodiment, and the description thereof will not be repeated.

Next, the operation will be described. In the third embodiment, the internal bus of the microcomputer 11 is also composed of two internal buses 36 and 61, thereby preventing an increase in current consumption and unnecessary radiation noise. Usually, microcomputer 1
1, the internal buses 36 and 61 are controlled by BIU.
(Bus interface unit) 62. Inside the microcomputer 11, a ROM 32 and a RAM
33, a dedicated bus for accessing at high speed, and a control bus different from the dedicated bus for controlling peripheral circuits and ports other than the memory are provided. Therefore, when the microcomputer 11 connects a memory having a built-in processing program, it is connected to a control bus, and there is a limit to speeding up access to the memory having a built-in processing program.
Accordingly, the internal bus is divided into two internal buses 36 and 61, and the internal bus 61, which is a dedicated bus, is connected to the flash memory 3 via the port 12 and the external bus 14, and the internal bus 36, which is a control bus, is connected. Is connected to the SRAM 4 and the G / A 5 via the port 13 and the external bus 15, so that the speed of access to the flash memory 3 having a built-in processing program can be easily increased.

As described above, according to the third embodiment, the internal bus of the microcomputer 11 also has two internal buses 36,
Since it is configured to be 61, it is possible to further prevent an increase in current consumption and unnecessary radiation noise. The internal bus 61, which is a dedicated bus, is connected to the flash memory 3 via the port 12 and the external bus 14, and the internal bus 36, which is a control bus, is connected to the SRAM 4 and G / G via the port 13 and the external bus 15. By connecting to A5, it is easy to speed up access to the flash memory 3 having a built-in processing program. Furthermore, in the first embodiment, the data buses that are not accessed are cut off in order to prevent the data bus values from colliding inside the microcomputer 11, but the internal buses are divided into two systems. Control can be made unnecessary.

[0023]

As described above, according to the present invention, when data is input or output to or from an external element connected to the selected external bus, the potential change is caused by the data of another system. It does not affect the bus and can prevent an increase in current consumption. Further, there is an effect that unnecessary radiation noise due to potential fluctuation can be prevented from affecting other external elements.

According to the present invention, when data is input or output to or from an external element connected to one of the selected external buses, the potential fluctuation affects the data bus of the other system. Therefore, an increase in current consumption can be prevented. Further, there is an effect that unnecessary radiation noise due to potential fluctuation can be prevented from affecting other external elements.

According to the present invention, even if the potential of one address bus fluctuates, the other address bus is not affected, and an increase in current consumption can be prevented.
Further, there is an effect that it is possible to prevent unwanted radiation noise from affecting the other system due to the potential fluctuation of one address bus.

According to the present invention, since the microcomputer has two internal buses, it is possible to further prevent an increase in current consumption and unnecessary radiation noise. Further, there is an effect that the control of shutting off the data bus for preventing the data bus value from colliding inside the microcomputer becomes unnecessary.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a multi-system bus control microcomputer according to a first embodiment of the present invention.

FIG. 2 is a conceptual diagram showing an internal configuration of a microcomputer.

FIG. 3 is a block diagram showing an external bus extension function of the microcomputer.

FIG. 4 is a block diagram showing a multi-system bus control microcomputer according to a second embodiment of the present invention.

FIG. 5 is a conceptual diagram showing an internal configuration of a microcomputer according to a third embodiment of the present invention.

FIG. 6 is a block diagram showing a conventional external bus control microcomputer.

[Explanation of symbols]

3 Flash memory (external device), 4 SRAM (external device), 5 G / A (external device), 11 microcomputer, 12, 13 port (external device connection terminal), 14, 15 external bus, 16, 19, 20 address bus, 17, 21 control bus, 18, 22 data bus, 36, 61 internal bus, 51, 53 bus latch circuit (address data fixing unit).

Claims (4)

[Claims] 1. A microcomputer having m sets (m is an arbitrary integer of 2 or more) of external element connection terminals, and n microcomputers (n is an arbitrary number of m or more) to which data is input or output by the microcomputer. (Integral) external elements and n sets of external element connection terminals and n external elements are classified into m systems and connected in accordance with the access frequency of the n external elements by the microcomputer. And an external bus comprising a control bus, a data bus and an address bus. The microcomputer selects one of the m external buses and transfers data with the external element connected to the external bus. A multi-system bus control microcomputer for performing input or output and cutting off the data bus of another system. 2. A microcomputer having two sets of external element connection terminals, a plurality of external elements to which data is input or output by the microcomputer, and a frequency of accessing the plurality of external elements by the microcomputer. An external bus consisting of a control bus, a data bus, and an address bus in which two sets of the external element connection terminals and the plurality of external elements are classified and connected in two systems; Selecting one of the external buses of the system to input or output data with the external element connected to the external bus, and shutting off the data bus of the other system. System bus control microcomputer. 3. The microcomputer according to claim 2, wherein the microcomputer includes an address data fixing unit for fixing the address data of the other address bus. 4. A microcomputer having two sets of external element connection terminals connected to two internal buses each comprising a control bus, a data bus and an address bus, and data is input or output by the microcomputer. A control bus in which two sets of the external element connection terminals and the plurality of external elements are classified into two systems and connected in accordance with a plurality of external elements and a frequency of access of the plurality of external elements by the microcomputer. , An external bus comprising a data bus and an address bus, wherein the microcomputer selects one of the two internal buses and the external bus from among the two systems and transmits data to the external element connected to the external bus. A multi-system bus control microcomputer characterized by performing input / output of the system.