KR920002073B1 - Data Memory Expansion Unit - Google Patents

Abstract

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Description

Data Memory Expansion Unit

1 is a block diagram of a conventional data memory expansion device using a bank (BANK) method.

2 is a schematic memory diagram of a memory expansion apparatus according to the present invention;

3 is a configuration diagram of a data memory expansion device according to the present invention.

* Explanation of symbols for main parts of the drawings

10: main memory 20: expansion memory

30: extended address generator A, B: address bus

DB: data bus

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data memory expansion device for use in a computer system or a single chip microcomputer requiring expansion of the data memory area, and more particularly, data limited by an address signal of a central processing unit (CPU). The present invention relates to a data memory expansion device capable of transferring data to and from data stored in main memory while expanding a memory area.

In general, in a computer system or the like, the address area of the data memory is limited by the number of address bits output from the CPU, that is, when the address bits are 16 bits, the total amount of available memory is limited to 2 ¹⁶ = 64K. The conventional data memory expansion device for overcoming such a contract uses a bank BANK method as shown in FIG. 1, which will be briefly described as follows.

As shown in FIG. 1, in the memory banks B1 to Bn + 1, an address signal and a data signal output from a central processing unit (not shown) are respectively provided through an address bus AB and a data bus DB. The memory banks B1 to Bn + 1 are applied to the write register SB and read signal SA, which are output from the central processing unit, and the bank register 1 to which data is set by the user. Data is written and read out in accordance with the combined signal output from the decoder 2 for decoding the output data. Therefore, when predetermined data is set in the bank register 1, the decoder 2 decodes it, selects one memory bank from among the plurality of memory banks B1 to Bn + 1, and the desired data in the selected memory bank. Write and read are used to expand the area of the data memory.

As described above, the data memory expansion device must change a value stored in the bank register 1 when the user wants to change the memory bank, and registers for controlling the data stored between the memory banks. Reads and writes the data stored in the memory bank of the memory bank, and transfers the data between banks using registers that transfer the written data to other memory banks, thereby increasing the number of instructions output from the central processing unit, thereby increasing the execution time. There was a lot of trouble.

Therefore, the present invention was created to solve the above-mentioned shortcomings, and expands the data memory irrespective of the limit of the number of address bits output from the central processing unit, and at the same time, mutual data through the data bus between the expanded memory and the main memory. The object of the present invention is to provide a memory expansion device for transmitting a.

In order to achieve the above object, the data memory expansion device according to the present invention uses a representative address (indicative of the size of the expansion memory) of one of the address signals output from the central processing unit (CPU) and an arbitrary address signal by means of a data signal. A memory allocation area is stored by an address generator which outputs (a signal specifying an address of data to be written or read out from the expansion memory) and an address signal output from the address generator, and data is written by the write and read signals. It is characterized in that it is configured as an extended memory for transmitting or reading data to and from the main memory and a data bus at the same time.

In the present invention, the form of the interconnection relationship between the extended memory and the main memory (serial and parallel connection) can be applied in any case according to the basic idea of the present invention.

Hereinafter, the present invention will be described in detail with reference to the drawings.

According to the memory expansion apparatus of the present invention, as shown in FIGS. 2 and 3, a write signal SB and a read signal SA, which are output from the CPU, are output from the CPU. Extended memory for writing and reading data input via the data bus DB by the output signal of the AND gates G1 and G2 combined with the signal according to a signal output from the address generator 30 to be described later ( 20) and generates an address signal according to one of the address signals (representative address) of the address signals output from the CPU and data applied through the data bus DB, and supplies them to the expansion memory 20. The address generator 30 and the main memory 10. At this time, the representative address and the later address occupy two addresses of the main memory. In the case of the parallel memory access method, since the representative address and the data address are required for each number of memory modules to be expanded in parallel, they occupy as many addresses as the number of 2x expansion memory modules of the main memory. In the case of using the serial method, since each expansion memory is connected to the main memory in a line, only two addresses will occupy each memory module and the main memory.

Referring to the operation relationship of the data memory expansion apparatus of the present invention as described above, first, when the user wants to use the expansion memory 20, the expansion address is first determined and then set in the address generator 30. In this state, the user stores predetermined data having a high frequency of use in the main memory 10 and stores data having a low frequency of use in the expansion memory 20, where the data is stored in the expansion memory 20. Is as follows.

That is, when the user inputs the corresponding data through the keyboard (not shown in the drawing) to store the data in the expansion memory 20, the CPU processes the address set in the expansion address generator 30. When the signal is supplied to the expansion memory 20, the data output from the CPU is applied to the address generator 30 through the data bus DB.

Accordingly, the expansion address generator 30 determines the output signal, that is, the address signal applied to the expansion memory 20, according to the applied data. On the other hand, the write signal SB applied to one terminal of the end gate G1 is in a high state, and the high signal is applied to the write terminal W of the expansion memory 20 so that the data bus DB is applied. Save data supplied through).

After the predetermined data is stored in the expansion memory 20 as described above, when the user inputs the data corresponding to the data stored in the main memory 10 of FIG. 2, the central processing unit (CPU) The read signal SA in the "high state" is output to make the expansion memory 20 read, and the address generator 30 is provided with the address signal and the data as the enable signal as described above. Accordingly, the expansion memory 20 reads data written in an area corresponding to the address signal applied from the address generator 30 and applies the data to the main memory 10 through the data bus DB, and the main memory 10. ) Is stored in the expansion memory 20, which is performed by a program stored in the central processing unit (CPU).

In the above-described expansion memory 20, a memory allocation area is determined by an address output from the address generator 30, and the total capacity of the expansion memory is

2 ⁿ × B

n: number of bits in address generator

B: number of bits in the system

Becomes

The memory expansion device of the present invention described above can freely expand the area of the data memory regardless of the limit of the number of address bits, and can also directly transfer data stored in the main memory and the expansion memory to each other, and has a short execution time. In systems with main memory, adding extended memory saves design time by eliminating the need to change the default layout.

Claims (1)

And gates G1 and G2 for combining each of the write signal SA and the read signal SB output from the CPU with the address signal output from the CPU; An expansion address generator (30) which outputs an arbitrary address signal by one of the address signals and data signals of the address signals output from the central processing unit; And a memory allocation area is designated by an address signal output from the expansion address generator 30, and writes and reads data by the write and read signals from the AND gate, and simultaneously through the data bus DB. Data memory expansion device comprising a main memory (10) and expansion memory (20) for transmitting data to each other.

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