JPH06150022A - Memory chip selection control circuit - Google Patents

Abstract

PURPOSE:To miniaturize a single chip microcomputer-mounted substrate and to omit the pins of an IC package without requiring any address decoder for chip selection signal generation and any dedicated output terminal for a chip selection signal for selecting an external memory chip from a single chip microcomputer. CONSTITUTION:An address decode circuit 8 is built in a single chip microcomputer 1 and generates a chip selection signal 9 from an address signal 7 for generating the chip selection signal of the external memory chip, and a switching circuit 11 selectively outputs an address signal 10 for specifying an access address inside the external memory chip and the chip selection signal 9 from an address/chip selection terminal 12 while switching the outputs of the chip selection signal 9 and the address signal 10.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to the selection of an external memory chip by a single chip microcomputer (hereinafter referred to as a single chip microcomputer) in which a CPU, an internal memory, an arithmetic circuit and an I / O port are integrated on the same substrate. Related to the circuit that controls.

[0002]

2. Description of the Related Art FIG. 7 is a block diagram of a portion related to a conventional memory chip selection of a single chip microcomputer.
When the single-chip microcomputer 1 selects a memory chip to be accessed from a plurality of external memories 2a, 2b, a part of the address signal of the external memory 2a or 2b output from the address output terminal of the single-chip microcomputer 1 is Address decoding circuits 8 and 8 provided outside are respectively decoded to activate the chip select signal 3 or 4 of either the memory 2a or 2b to be accessed. The selected memory 2a or 2b fetches the address signal 6 for specifying the access address in the memory 2a or 2b, and the data signal 5 is transferred between the memory 2a or 2b and the single-chip microcomputer 1.
Is transferred.

Further, as shown in FIG.
In the case of the single-chip microcomputer 1 incorporating 8 and 8, the single-chip microcomputer 1 is provided with dedicated terminals for outputting the chip select signals 3 and 4.

Further, FIG. 9 shows the output of a part of the address signal and the data signal as a control signal ALE (Address
FIG. 11 is a block diagram of a conventional portion related to memory chip selection of a single-chip microcomputer which is switched by a Latch Enable) and output from a dual-purpose terminal. The same portions as those described above are designated by the same reference numerals and the description thereof will be omitted. In the figure, 19 is ALE
Signals, 20a to 20d are latches, 21 is a data signal, 22a to 22
d is the data whose output is switched by the ALE signal 19
The address signal is output from the shared terminal.

Some of the address signals 22a to 22d switched and output from the single-chip microcomputer 1 from the dual-purpose terminals are held in the latches 20a to 20d by the rising and falling edges of the ALE signal 19 input to the terminals T of the latches 20a to 20d. To be done. Latch 20a, 20b at next rising edge of ALE signal 19
Data held in the memory 2a or 8 is output to the address decoding circuits 8 and 8 and decoded respectively. As a result, either the chip select signal 3 or 4 becomes active and the memory 2a or
2b is selected.

The data held in the other latches 20c and 20d is output to the address bus to specify the access address in the memory 2a or 2b together with the remaining address signal 6. After the address signals 22a to 22d are held in the latches 20a to 20d, the data signals 21, 22a to 22d are transferred from the single chip microcomputer 1 to the memories 2a and 2b via the shared terminals.

[0007]

The conventional memory chip selection between the single-chip microcomputer and the plurality of external memories is realized by the above configuration, and the memory chip to be accessed is selected from the plurality of external memory chips. Since an address decode circuit for selecting is to be provided externally, the board becomes large when the gate IC of the address decode circuit and the like are mounted on the same board.

However, when the address decoding circuit is built in the single-chip microcomputer, the single-chip microcomputer must be provided with a dedicated output terminal for the chip select signal, so that the IC package of the single-chip microcomputer has a large number of pins and the manufacturing cost increases. .

The present invention has been made in order to solve such a problem. A chip select signal for selecting an external memory chip is generated inside a CPU-mounted chip and the chip select signal is used as an address signal. It is an object of the present invention to provide a memory chip selection control circuit which does not require an external address decode circuit and which does not require an output terminal dedicated to a chip select signal.

[0010]

A memory chip selection control circuit according to a first aspect of the present invention includes a circuit which is built in a chip having a CPU and which generates a chip select signal for an external memory chip, and a chip from an address output terminal. And a circuit for switching the output of the select signal and the address signal.

A memory chip selection control circuit according to a second aspect of the present invention includes a circuit which is built in a chip on which a CPU is mounted and which generates a chip select signal for an external memory chip.
And a circuit for switching output of a chip select signal, an address signal, and a data signal from the data / address dual-use terminal.

[0012]

When the CPU specifies the address of the external memory chip to be accessed, the memory chip select control circuit according to the first aspect of the present invention outputs a chip select signal for selecting the external memory chip to be accessed based on this address. It is generated and the output from the address output terminal is switched to the output of the chip select signal, and the chip select signal is output from the address output terminal.

In the memory chip selection control circuit according to the second invention, when the CPU designates the address of the external memory chip to be accessed, a chip select signal for selecting the external memory chip to be accessed based on this address is sent. Generate and switch the output from the data / address dual-purpose terminal to the output of the chip select signal.
A chip select signal is output from the address shared terminal.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings showing its embodiments. FIG. 1 is a block diagram of a single chip microcomputer incorporating a memory chip selection control circuit according to the present invention and an external memory, and FIG. 2 is a block diagram of the memory chip selection control circuit according to the present invention corresponding to one terminal.
Note that the same or corresponding portions as those of the conventional one are designated by the same reference numerals and the description thereof will be omitted.

In the figure, 7 is a chip select address signal for designating the memory 2a or 2b, 9 is a chip select signal generated by the address decoding circuit 8, and 10 is an address for specifying an access address in the memories 2a and 2b. 1-bit address signal of the signal, 11 is a switching circuit for switching the output of the chip select signal 9 and the address signal 10, 12 is a part of the address terminal and also serves as the output terminal of the chip select signal 3 (4) Address / chip select terminal. The shared terminal is an address output terminal excluding an output terminal corresponding to the number of bits of the address signal in which the required number of bits is determined according to the capacities of the memories 2a and 2b and the number of connections.

FIG. 3 is a specific circuit diagram of the address decoding circuit 8 described above. The address register 13 stores the address of the memory 2a or 2b selected when the chip select signal from that terminal becomes active.
The memory capacity register 14 has a single chip microcomputer 1
Among the address signals output from the address output terminal provided in, the output corresponding to the bit number of the address signal whose required bit number is determined according to the capacity and the number of connections of the memories 2a and 2b is set to "H", and these Data in which the bit output of the upper address corresponding to the output / terminal of the chip select signal except the bit is set to "L" is stored.

For example, assuming that the address output terminals provided in the single chip microcomputer 1 are 20 and the capacities of the memories 2a and 2b are 64 Kbytes, the address when two memories 2a and 2b are connected requires 17 bits. Therefore, the three address output terminals corresponding to the higher-order address also serve as the output of the chip select signal, and the memory capacity register 14 has 3 bits from the most significant "L" and the other bits "H".
The data set in is stored.

The EXOR gates 15a to 15c use the bit value of the 3-bit chip select address signal 7 as one input and the bit value of the address stored in the address register 13 as the other input. To do. The NAND gates 16a to 16c use the outputs of the EXOR gates 15a to 15c as one input, and the memory capacity register 14
Of the output of, the value for the most significant 3 bits, that is,
Let “L” be the other input of each. Also NAND gate
16d outputs the chip select signal 9 to the switching circuit 11 with the outputs of the NAND gates 16a to 16c as three inputs.

FIG. 4 is a specific circuit diagram of the switching circuit 11.
The first NAND gate 16e receives the chip select signal 9 from the address decoding circuit 8 as one input, and receives the inverter 17
The inverted signal of the address / chip select switching signal 18 by a is used as the other input. The second NAND gate 16f receives the address / chip select switching signal 18 as one input and the address signal 10 as the other input. Furthermore, the third
The NAND gate 16g receives the outputs of the NAND gates 16e and 16f as two inputs and outputs the chip select signal / address signal 3 (4) from the address / chip select terminal 12.

When the address / chip select switching signal 18 is "H", the address / chip select terminal 12
Outputs an address signal 10, and when the address / chip select switching signal 18 is "L", the address / chip select terminal 12 outputs a chip select signal 9.

Next, the operation will be described. Not shown
The EXOR gates 15a to 15c compare the chip select address signal 7 of the memories 2a and 2b designated by the CPU with the address stored in the address register 13, and when the comparison result is coincident, that is, the chip select from this terminal When the memory 2a or 2b selected by the signal 9 is designated, all the outputs of the EXOR gates 15a to 15c become "L". In addition, NA
The ND gates 16a to 16c take the logical product of the output "L" of the EXOR gates 15a to 15c and the "L" of the upper 3 bits of the memory capacity register 14, and the outputs of the NAND gates 16a to 16c are all "H". Becomes As a result, the chip select signal 9 output from the NAND gate 16d becomes "L".

Address / chip select switching signal 18
Is "L" and the chip select signal 9 is "L", the output of the first NAND gate 16e is "H", and the output of the second NAND gate 16e is "H".
Since the output of the gate 16f also becomes "H", the output of the third NAND gate 16g becomes "L" and the chip select signal 3 (4) output from the address / chip select terminal 12 becomes active.

When the address / chip select switching signal 18 is "L" and the chip select signal 9 is "H", the output of the first NAND gate 16e is "L",
Since the output of the second NAND gate 16f becomes "H",
The output of the NAND gate 16g becomes "H" and the chip select signal is output from the address / chip select terminal 12.
3 (4) is non-active.

On the other hand, when the address / chip select switching signal 18 is "H", the chip select signal 9 is "H".
The output of the first NAND gate 16e becomes "H" regardless of "L", so that the value of the address signal 10 becomes the second NA.
Inverted by ND gate 16f, and the third NAND gate
Inverted by 16g, resulting in the original address signal 10
Is output from the address / chip select terminal 12.

FIG. 5 is a block diagram of a single-chip microcomputer having a data / address / chip select signal switching structure incorporating a memory chip selection control circuit according to the present invention, and FIG. 6 is a memory chip selection control circuit according to the present invention. It is a concrete circuit diagram of a switching circuit. The same or corresponding parts as those in the above-described embodiment are designated by the same reference numerals and the description thereof will be omitted. In the figure, 22a to 22d are switched and output from the dual-purpose terminals, but data / address / chip select signals, 23a and 23b are chip select signals, 24 is a data / address / chip select switching signal, 25 is a data signal, and 26 is a dual-purpose terminal. Is a data / address / chip select signal that is output by switching from.

The first NAND gate 16h inverts the chip select signal 9 from the address decoding circuit 8, the inverted signal of the address / chip select switching signal 18 by the inverter 17b, and the inversion of the data / address / chip select switching signal 24 by the inverter 17c. 3 signals are input.
The second NAND gate 16i receives the address / chip select switching signal 18, the address signal 10, and the inverted signal of the data / address / chip select switching signal 24 by the inverter 17c as three inputs. The third NAND gate 16j receives the data signal 25 as one input and the data / address / chip select switching signal 24 as the other input. further,
The fourth NAND gate 16k receives the outputs of the NAND gates 16h, 16i and 16j as three inputs and selectively outputs the data / address / chip select signal 26 from the shared terminal of the single chip microcomputer 1.

When the data / address / chip select signal 24 is "H", the data / address / chip select signal 26 is switched to the output of the data signal 25. Also, the data / address / chip select signal 24 is "L".
When the address / chip select switching signal 18 is "H", the data / address / chip select signal 26
Is switched to the output of the address signal 10. Further, the data / address / chip select signal 24 is "L" and the address / chip select switching signal 18 is "L".
At this time, the data / address / chip select signal 26 is switched to the output of the chip select signal 9.

Next, the operation will be described. When the data / address / chip select signal 24 is "L" and the address / chip select switching signal 18 is "L",
The output of the first NAND gate 16h becomes "H" or "L" in response to the "L" or "H" of the chip select signal generated by the address decoding circuit 8 in the same manner as the above-mentioned embodiment.
Since the output of the second NAND gate 16i is "H" and the output of the third NAND gate 16j is "H", the fourth NAND gate 16i
The output of k becomes "L" or "H" of the chip select signal 9, and the data / address / chip select signal 26 is switched to the output of the chip select signal 9.

When the data / address / chip select signal 24 is "L" and the address / chip select switching signal 18 is "H", the output of the first NAND gate 16h is "L" of the chip select signal. Since the output of the third NAND gate 16j is "H" regardless of "H" and the output of the third NAND gate 16j is "H", "L" of the address signal 10 inverted by the second NAND gate 16i is the fourth. NAND gate 16k again inverts the data / address / chip select signal 26
Switches to the output of address signal 10.

When the output of the third NAND gate 16j becomes "H", the CPU outputs the ALE signal 19, and the output signal (chip select or address signal) is latched by the rising and falling of the ALE signal 19. Latched to 20d.

On the other hand, when the data / address / chip select signal 24 is "H", the first and second signals are set regardless of whether the address / chip select switching signal 18 or the chip select signal 9 is "H" or "L". Since the outputs of the NAND gates 16h and 16i are "H", the "H" and "L" of the data signal 25 inverted by the third NAND gate 16j are inverted again by the fourth NAND gate 16k and the data / The address / chip select signal 26 switches to the output of the data signal 25.

The address decoding circuit 8 and the switching circuit
11 is not limited to the logical configuration of this embodiment.

[0033]

As described above, the memory chip selection control circuit of the present invention is built in a chip on which a CPU is mounted to generate a chip select signal of an external memory chip, and an address output terminal or a data / address dual-purpose terminal. Since there is no need to provide an address decode circuit externally, and there is no need for a dedicated output terminal for the chip select signal, it is possible to achieve pin-saving of the IC package.

[Brief description of drawings]

FIG. 1 is a block diagram of a single chip microcomputer with a built-in memory chip selection control circuit and an external memory according to the present invention.

2 is a block diagram of a memory chip selection control circuit according to the present invention incorporated in the single chip of FIG. 1. FIG.

FIG. 3 is a circuit diagram of an address decode circuit which constitutes a memory chip selection control circuit according to the present invention.

FIG. 4 is a circuit diagram of a switching circuit which constitutes a memory chip selection control circuit according to the present invention.

FIG. 5 is a block diagram of an external memory and a single-chip microcomputer having a structure that also serves as a data / address / chip select signal terminal having a built-in memory chip selection control circuit according to the present invention.

FIG. 6 is a circuit diagram of a switching circuit included in the single chip microcomputer of FIG. 5, which constitutes a memory chip selection control circuit according to the present invention.

FIG. 7 is a block diagram of a portion related to a conventional memory chip selection between a single chip microcomputer and an external memory.

FIG. 8 is a block diagram of a portion related to a conventional memory chip selection between a single-chip microcomputer including an address decoder and an external memory.

FIG. 9 is a block diagram of a portion related to a conventional memory chip selection between a single-chip microcomputer also serving as an address / data signal terminal and an external memory.

[Explanation of symbols]

 1 Single-chip microcomputer 2a, 2b Memory 3, 4 Chip select signal 5 Data signal 6 Address signal 7 Chip select address signal 8 Address decode circuit 9 Chip select signal 10 Address signal 11 Switching circuit 12 Address / chip select terminal 13 Address register 14 Memory Capacity register 18 Address / chip select switching signal 19 ALE signal 20a to 20d Latch 21 Data signal 22a to 22d Data / address / chip select signal 23a, 23b Chip select signal 24 Data / address / chip select switching signal 25 Data signal 26 data / Address / chip select signal

Claims (2)

[Claims] 1. A circuit for controlling selection of an external memory chip by a chip mounting a CPU, comprising:
A circuit which is built in a chip on which U is mounted and which generates a chip select signal for selecting an external memory chip to be accessed from a plurality of external memory chips based on the address of the external memory chip to be accessed specified by the CPU. And a circuit for switching the output of the address signal and the chip select signal so as to output the chip select signal from the address output terminal of the chip on which the CPU is mounted. 2. The output of the address signal and the data signal is C
In a circuit that controls selection of an external memory chip by a chip that is switched according to a control signal from a PU and selectively outputs from a shared terminal of a chip on which a CPU is mounted, the circuit is built in the chip on which the CPU is mounted and specified by the CPU A circuit for generating a chip select signal for selecting an external memory chip to be accessed from a plurality of external memory chips based on an address of the external memory chip to be accessed, and a chip select signal to be output from the dual-purpose terminal , A circuit for switching the output of a data signal, an address signal, and a chip select signal, and a memory chip selection control circuit.