JPH0628307A - Bus controller - Google Patents

Abstract

PURPOSE:To provide a bus controller which can attain the interchangeability and the high speed performance of buses regardless of a system of the specific specifications by using means which performs the optional switching of bus interfaces of different specifications such as the standardization and the high speed performance, etc. CONSTITUTION:A bus switching control circuit 2 selects a standardized bus interface or a high speed bus interface. A PI bus basic signal generating circuit 2a produces a PI bus cycle basic signal, and an ISA bus basic signal generating circuit 2b produces an ISA bus cycle basic signal. A memory I/O control circuit 5 outputs an access control signal in response to the bus cycle timing of a PI or ISA bus interface, based on the PI or ISA bus cycle basic signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus control device for controlling a bus interface used in a personal computer in particular.

[0002]

2. Description of the Related Art Conventionally, in a computer system such as a personal computer, some of the various units forming the system are compatible only with a bus interface having a predetermined specification. For example, ISA (Indust
If a standardized bus interface called a “ry Standard Architecture” bus is frequently used, a display controller (for example, VGA of IBM company specification) corresponding to only the ISA bus is used.

By the way, in order to speed up the bus cycle, for example, PI (Periph-eral Inte) is used.
A bus interface with a high-speed access specification has been developed, which is called "rface) bus". Some systems support both high-speed access PI bus interface and standardized ISA bus interface,
A system that can ensure high speed and compatibility of bus cycle timing (for example, CP of 80386SL type manufactured by Intel Corporation)
U) has been developed.

PI for the display controller and the like
It may be possible to increase the speed by making it compatible with the bus.
If only the I bus is supported, there is a problem that the bus compatibility with the ISA bus cannot be ensured. In order to ensure bus compatibility, it depends on a system capable of ensuring high speed and compatibility of bus cycle timing as described above, and cannot be applied to other systems.

[0005]

Conventionally, a unit such as a display controller, which is compatible only with a standardized bus interface having a predetermined specification, is often used as a component of a computer system. In order to increase the speed of such a unit, it may be possible to support a high-speed access specification bus interface, but it is not possible to ensure bus compatibility with a standardized bus interface. In this case, in order to satisfy both characteristics of high speed and compatibility, it depends on only the system having both characteristics, and there is a problem that the applicable range of the unit is limited.

An object of the present invention is to provide bus compatibility and high speed without depending on a system of a specific specification by having means for arbitrarily switching bus interfaces of different specifications such as standardization and high speed. It is to provide a bus control device that can be realized.

[0007]

SUMMARY OF THE INVENTION The present invention provides bus switching means for selecting and designating bus interfaces having different bus cycle timings, bus cycle basic signal generating means for outputting a bus cycle basic signal corresponding to a selected bus interface, and It is a bus control device having access control means for outputting an access control signal of an access target based on a bus cycle basic signal.

[0008]

In the present invention, the bus switching means selects, for example, one of the standardized bus interface and the high speed bus interface. The bus cycle basic signal generating means outputs a bus cycle basic signal corresponding to the standardized or high speed bus interface selected by the bus switching means. The access control means outputs an access control signal corresponding to the bus cycle timing of the selected standardized or high-speed bus interface to a unit such as a memory based on the bus cycle basic signal generated by the bus cycle basic signal generation means. To do.

[0009]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a configuration of a bus control device according to the embodiment, FIG. 2 is a block diagram showing a main part of a computer system according to the embodiment, and FIG. FIG. 4 is a timing chart of the memory write mode for explaining the operation of the embodiment.

As shown in FIG. 1, the present bus control device comprises a bus signal selection circuit 1, a bus switching control circuit 2, an address decoder 3, a data bus control circuit 4, and a memory / I / O control circuit 5. There is. The bus signal selection circuit 1 uses a bus switching signal BS from a system CPU, for example, to provide a high-speed bus interface (here, PI bus) or a standardized bus interface (here, IS).
One bus control signal group (A bus) is selected and output to the bus switching control circuit 2.

The bus switching control circuit 2 generates a PI bus basic signal generation circuit 2a and an IS for generating a PI bus cycle basic signal in response to an input of a PI bus bus control signal group.
It has an ISA bus basic signal generation circuit 2b for generating an ISA bus cycle basic signal in response to an input of a bus control signal group of the A bus. PI bus cycle basic signal and I
The SA bus cycle basic signal is an access control signal and I corresponding to the bus cycle timing of the PI bus.
This is a basic signal for generating an access control signal according to the bus cycle timing of the SA bus.

The bus switching control circuit 2 has a function of executing READY control, data setup control and timing control in addition to the basic signal generation function. Specifically, the memory chip select signal (MEMCS16) and the I / O chip select signal (IOCS16) are output according to the bus control signal group of the ISA bus. MEMCS
Reference numeral 16 is an active "L" signal indicating that valid data transfer on the ISA bus is a 16-bit memory cycle. On the other hand, IOCS 16 is an active "L" signal indicating that valid data transfer on the ISA bus is a 16-bit I / O cycle. The bus switching control circuit 2 is P
The I bus cycle basic signal or the ISA bus cycle basic signal is applied to the data bus control circuit 4 and the memory / I / O control circuit 5.
Output to both.

The data bus control circuit 4 responds to the PI bus cycle basic signal or the ISA bus cycle basic signal according to
Timing control of data (D15-00) transfer of the system data bus 10 is performed according to the bus cycle timing of the PI bus or ISA bus. Based on the PI bus cycle basic signal or the ISA bus cycle basic signal, the memory / I / O control circuit 5 responds to the bus cycle timing of the PI bus or ISA bus, or the memory or I / O of the I / O cycle. It is a circuit that generates an access control signal.

The address decoder 3 decodes the address (A23-00) transferred through the system address bus 11 and outputs a decoded signal to the bus switching control circuit 2. The address decoder 3 uses the bus control signal P of the PI bus.
It has a latch circuit 3a for latching an address transferred through the address bus 11 in response to START. P
The START signal is a PI bus cycle start signal and indicates that the chip select signal of the address bus 11 or the display controller (here, VGA) is valid. The common bus control signal SBHE of the PI bus and the ISA bus is input to the address decoder 3. This SBHE (System Byte High Enab)
The le) signal is an active “L” signal indicating that the data transferred on the data bus 10 is the upper byte. The SBHE signal is also input to the bus switching control circuit 2. Next, the operation of the embodiment will be described.

In the embodiment, as shown in FIG.
It is assumed that the computer system 13 and the display controller 14 are connected by a bus interface. The bus interface is the system data bus 1
0, a system address bus 11, and a control bus 12 for transferring a bus control signal group. The display controller 14 executes the VRAM read / write mode under the control of the CPU 13.

In this embodiment, the case where the display controller 14 is in the VRAM write mode will be described. As shown in step S1 of FIG. 3, one of the ISA bus and the PI bus is selectively designated by the bus switching signal BS from the CPU 13.

The bus signal selection circuit 1 includes a bus switching signal BS.
When the ISA bus is selected according to (YES in step S1
S), a bus control signal group of the ISA bus is selected and output to the bus switching control circuit 2. Here, the bus control signal group of the ISA bus includes a MEMW (Memory Write) signal, a MEMR (Memory Read) signal, and an IOW.
(I / O Write) signal, IOR (I / O Rea)
d) signal, AEN (Address Enable) signal and the like. The MEMW signal is an active “L” signal for instructing a memory (here, VRAM) to write data to be transferred on the data bus 10. The MEMR signal is an active "L" signal for instructing the memory to transfer and drive the data from the memory on the data bus 10. The IOW signal and the IOR signal are the MEMW signal and the MEM when the target is changed from the memory to the I / O unit.
It is a signal corresponding to the R signal. The AEN signal is an active "H" signal for designating a DMA cycle in which the DMA controller controls (occupies) the system address bus 11.

Here, since it is the case of the memory write cycle by the ISA bus, as shown in FIG.
The bus control signals of the MEMW signal of the logic level “L” and the AEN signal of the logic level “L” are supplied to the bus switching control circuit 2.

In the bus switching control circuit 2, the ISA bus basic signal generating circuit 2b operates to generate an ISA bus cycle basic signal (step S2). At this time, the PI bus basic signal generation circuit 2a is in a stopped state. As shown in FIG. 4A, the bus switching control circuit 2 outputs a signal MEMCS16 having a logic level "L" indicating that valid data transfer on the ISA bus is a 16-bit memory cycle.

The address decoder 3 includes an address bus 11
The address transferred at is decoded and the decoded signal is output to the bus switching control circuit 2 (steps S3 and S4).
At this time, in the ISA bus, before the MEMW signal is output, the data bus 10, the address bus 11 and the AEN
Since the signal is fixed, it is not necessary to hold the bus control signal during the bus cycle.
It is output to the memory / I / O control circuit 5 without being latched by a.

The bus switching control circuit 2 determines that the memory or I / O is accessed by the decode signal from the address decoder 3, and the ISA bus basic signal generation circuit 2
The ISA bus cycle basic signal generated by b is output (step S5). The memory / I / O control circuit 5
Based on the ISA bus cycle basic signal, an access control signal for the memory cycle corresponding to the bus cycle timing of the ISA bus is generated (step S6). In this embodiment, the access control signal controls the write access of the VRAM, and the write operation of the data transferred by the data bus 10 is executed. Here, the data bus control circuit 4 controls the timing of the data bus 10 according to the ISA bus cycle timing by the bus control signal in the ISA bus cycle basic signal.

When the memory cycle ends, the memory / I / O control circuit 5 outputs a READY signal to the bus switching control circuit 2. The bus switching control circuit 2 executes READY control according to the ISA bus in response to the READY signal. Here, in the case of an I / O cycle, the bus switching control circuit 2
As shown in FIG. 4 (A), IOCHRDY (I / O
Channel Ready) signal is output. IO
The CHRDY signal indicates that the IS
This is an active "H" signal for indicating that the I / O unit accessed by the A bus is Ready.

On the other hand, when the bus signal selection circuit 1 selects the PI bus according to the bus switching signal BS (NO in step S1), the bus control signal group of the PI bus is selected and output to the bus switching control circuit 2. . Here, the bus control signal group of the PI bus includes PM / IO (PI-bus Memory).
or I / O) signal, PW / R (PI-busWrit)
e or Read signal, PCMD (PI-bus)
Command) signal or the like. The PM / IO signal is a signal for designating a memory cycle at a logic level "H" and designating an I / O cycle at a logic level "L". PW /
The R signal is a signal for instructing write access at a logic level “H” and for instructing read access at a logic level “L”. The PCMD signal is an active “L” signal for instructing that the data transferred on the system data bus 10 is valid.

Since the memory write cycle is based on the PI bus here, as shown in FIG. 4B, the PM / IO signal of the logic level "H", the PW / R signal of the logic level "H", and The bus control signal of the PCMD signal of the logic level “L” is supplied to the bus switching control circuit 2.

In the bus switching control circuit 2, the PI bus basic signal generating circuit 2a operates to generate a PI bus cycle basic signal (step S7). At this time, the ISA bus basic signal generation circuit 2b is in an operation stopped state.

The address decoder 3 includes an address bus 11
The address transferred at is decoded and the decoded signal is output to the bus switching control circuit 2 (step S9). At this time, on the PI bus, the address is fixed before the PSTART signal is output. However, the address bus 11 becomes the address for the next access within a few ns after the PSTART signal is output. Therefore, in the address decoder 3, as shown in FIG.
The latch circuit 3a holds the address from the address bus 11 by the T signal (step S8).

The bus switching control circuit 2 determines that the memory or I / O is accessed by the decode signal from the address decoder 3, and the PI bus basic signal generation circuit 2a.
The PI bus cycle basic signal generated by is output (step S10). The memory / I / O control circuit 5 has a P
Based on the I bus cycle basic signal, an access control signal for the memory cycle corresponding to the bus cycle timing of the PI bus is generated (step S11). In this embodiment, the access control signal controls the write access of the VRAM, and the write operation of the data transferred by the data bus 10 is executed. Here, the data bus control circuit 4 controls the timing of the data bus 10 according to the PI bus cycle timing by the bus control signal in the PI bus cycle basic signal.

When the memory cycle is completed, the memory / I / O control circuit 5 outputs a READY signal to the bus switching control circuit 2. The bus switching control circuit 2 executes READY control according to the PI bus according to the READY signal. That is, the bus switching control circuit 2, as shown in FIG.
PRDY (PI-busRead) of logic level "L"
y) Output the signal. The PRDY signal indicates the end of the bus cycle.

In this way, the standardized ISA bus interface and the high-speed PI bus interface can be arbitrarily switched to correspond to the bus interface in which a unit such as a display controller is selected and designated. Therefore, in the standardized specifications, depending on the bus cycle timing of the ISA bus interface,
Memory or I / O access control can be performed. On the other hand, in the high-speed access specification, access control of the memory or I / O can be performed at high speed according to the bus cycle timing of the PI bus interface. In other words, without relying on a specific system,
It is possible to achieve high speed and ensure bus compatibility with a standardized ISA bus interface for a system that does not support the PI bus interface.

[0031]

As described above in detail, according to the present invention, a bus having standard bus cycle timing and high speed bus cycle timing can be used by arbitrarily switching bus interfaces having different specifications such as standardization and high speed. Control can be realized. Therefore, it is possible to speed up data transfer without depending on a system of a specific specification, and to ensure bus compatibility with a system that only supports a conventional standardized bus interface.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a bus control device according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a main part of a computer system according to the first embodiment.

FIG. 3 is a flowchart for explaining the operation of the embodiment.

FIG. 4 is a timing chart of a memory write mode for explaining the operation of the embodiment.

[Explanation of symbols]

1 ... Bus signal selection circuit, 2 ... Bus switching control circuit, 3 ... Address decoder, 5 ... Memory / I / O control circuit.

Claims (1)

[Claims] 1. A bus switching means for selectively designating a bus interface having a different bus cycle timing, and a bus cycle basic signal generating means for outputting a bus cycle basic signal corresponding to the bus interface selected by the bus switching means, Access control means for outputting an access control signal to be accessed according to the bus cycle timing of the selected bus interface based on the bus cycle basic signal generated by the bus cycle basic signal generation means. Characteristic bus control device.