JPH02253362A - Data transfer system between microprocessor and fifo buffer - Google Patents

Abstract

PURPOSE:To transfer data at a high speed by mapping the address of a FIFO buffer to an address set on the boundary of a long word of a microprocessor with lower 2 bits of the latter address neglected. CONSTITUTION:The address of a FIFO buffer contained in a small computer system interface protocol controller 202 is mapped to an address set on the boundary of a long word of a microprocessor 201 in disregard of lower 2 bits of the latter address. Then an access is given to the FIFO buffer in a data size larger than the width of a data bus 205 set between the microprocessor 201 and the FIFO buffer. As a result, the bus sizing function of the processor 201 works and the data having the number of bits corresponding to the width of the data bus can be continuously transferred in the frequency corresponding to the access size just with a single access. Thus the data can be transferred at an extremely high speed without using any special hardware like a DMA.

Description

Detailed Description of the Invention <Industrial Application Field> The present invention relates to a microprocessor and a FIFO (FIFO) buffer when the microprocessor transfers data between the microprocessor and another device via a FIFO (fast-in-fast-out) buffer.
It relates to a data transfer method to and from a buffer.

<Prior art> When a microprocessor transfers data with another device, a PIF'O buffer mapped to a certain address of the microprocessor is used to alleviate constraints such as timing caused by the difference in processing speed between the two devices. Do it through. At this time, since the width of the data bus of the FIFO buffer is generally 8 bits, the microprocessor transfers data byte by byte to and from the FIFO buffer by byte access.

<Problems to be Solved by the Invention> However, in the above-mentioned byte access method, when transferring data of n bytes (n=1,'2,3,...), the microprocessor must store at least one data in the PIF'O buffer. It must be accessed n times (at least 21 times if the status of the F'IPO buffer needs to be checked), which is extremely time consuming when handling a large amount of data such as image data.

On the other hand, there is a method of adding a DMAC (Direct Memory Access Controller) to achieve high-speed data transfer, but this requires special hardware.
This poses a problem in terms of cost.

SUMMARY OF THE INVENTION An object of the present invention is to provide a data transfer method between a microprocessor and a FIFO buffer that can transfer data at high speed without requiring special hardware such as DMA.

Means for Solving the Problems> To achieve the above object, the present invention uses a microcomputer having a bus sizing function. Bus sizing means that microprocessors are 8.16 and 3
The bit width of a 2-bit port is detected, and a predetermined number of cycles are performed according to the bit width as shown in Fig. 1 (a) and (b).
, as shown in (c), is to transfer operands to and from the boat. For example, if you are executing an instruction that requires reading a longword (32 bits) operand, the microprocessor will attempt to read the 32 bits on the first bus cycle. If the port responds that the bus width is 32 bits, the microprocessor outputs the data (ByteO-Bytea) as shown in Figure 1(a).
) into the data register at once and continue with the next operation. If the port responds with a 16-bit bus width, the microprocessor will
), 16 bits of valid data (ByteO-Bytel) are latched in one cycle, and another cycle is executed to obtain the other 16-bit data (Byte2-Bytea).

An 8-bit vote is treated similarly as shown in FIG. 1(c), but in this case there are four read cycles.

In addition, in Figure 1, the X mark is any hexadecimal number (0 to r
).

Therefore, the data transfer method between the microprocessor and the FIFO buffer of the present invention is based on the microprocessor's address (x x x xxxxO, xx
xxxxxx4. xxxxxxxx8゜xxxxxxxxc,
Here, x represents any hexadecimal number (0 to r). Hereinafter, this address will be assumed to be an address on the longword boundary. ), this method is possible even if the FIFO bus is mapped by ignoring the lower 2 bits of the address and the lower 3 bits, 4 bits, etc. are ignored, but the number of bits increases. This results in a lot of wasted memory. ), the bus sizing function of the microprocessor is used by accessing the FIFO bus with a data size greater than the data bus width between the microprocessor and the PIF'O buffer.

In this data transfer method, when a microprocessor with a bus sizing function transfers data to another device via a FIFO buffer, the address of the F'lFO buffer is placed on the longword boundary of the microprocessor. F'I is mapped to a certain address while ignoring the lower two bits of that address, and F'I is mapped to a certain address with a data size that is greater than the data bus width between the microprocessor and the F
Accessing the FO buffer provides data transfer between the microprocessor and the FIFO buffer. At this time, the microprocessor's bus sizing function works, and in one access, data of the number of bits corresponding to the width of the PIFO buffer is transferred continuously on the data bus of the PIFO buffer a predetermined number of times according to the access size. The data can be transferred faster than accessing the data a predetermined number of times.

Also, when it is necessary to check the status of the FIFO buffer, the specified number of times x 1 byte or the specified number of times x n bytes (n
-2, 3, 4...), which leads to faster speeds.

<Example> Hereinafter, the present invention will be explained in detail with reference to illustrated embodiments.

In FIG. 2, a microprocessor (hereinafter referred to as MP[J) 201 having a bus sizing function is 1.
5PC (Small Computer System Interface Protocol Control) with FIFO buffer
ler)) 202, data is transferred to and from the hard disk 203. 5PC202 addresses aO to a3 (MSB:a3.LSB:aO) have MPU
The address lines A2 to A5 of the address bus 204 of the MPU 201 are connected, and the 5PC 202 is mapped to an address on the boundary of the long word of the MPU 201. address line AI
and AO are ignored. It is assumed that the 5PC 202 and the hard disk 203 are connected by a 5CSI (Small Computer System Interface) path 206, and data transfer between the two is performed according to the 5CSI protocol. The bit width of the data bus 205 between the MPU 201 and the 5PC 202 is 8 bits.

Data transfer between the MPU 201 and the 5PC 202 is performed by the MPU 201 making longword access to the 5PC 202. As a result, MPU20
The bus sizing function of 1 works, and 5
Four bytes of data are continuously transferred on the 8-bit data bus 205 of the PC 202.

The state of reading from the FIFO buffer by the above method will be explained with reference to FIG. Here, it is assumed that the PIFO buffer is mapped to address xxxxxxxxO. × represents any hexadecimal number (0 to f).

Figure 3(a) is the first read cycle, when the MPU20
1 makes a longword access to address xxxxxxxxO, that is, the FIFO buffer, the bus sizing function is activated, and the contents of address xxxxxxxxo,
In other words, the first data on the MPU side of the FIFO buffer (
DataO (88 bits) is stored in the most significant byte (D31D24) of the data register. When the first data of the PIF'O buffer is read, the following data is
The IFO buffer is shifted one by one forward (to the MPU side). This operation is similar in each subsequent read cycle.

Figure 3(b) shows the second read cycle, when the MPU20
The address bus 205 of No. 1 is xxxxxxxl, but
The lowest two bits are ignored, so xxxxxxx again
It will access O.

xxxxxxxo will be accessed in the same way in each subsequent cycle. Here, the data at the head of the FIFO buffer, ie, data (Data), is stored in the second byte (D23-D16) of the data register.

Figure 3(C) shows data (D) during the third read cycle.
ata2) is the third byte of the data register (Di5-D
8) Stored in the eyes.

Figure 3(d) shows data (D
ata3) is the lowest byte of the data register (D7-D
o), and reading from the MPU 201 to the PIF'O buffer by one longword access is now complete. In this way, 4 bytes of data can be read out continuously on the 8-bit data bus 205 in one access.

FIG. 4 shows how data is written to the FIFO buffer. This write is also performed from the data register of the MPU 201 to the F by the bus sizing function of the MPU 201.
Using the 8-bit data bus 205 to the IFO buffer, 4 bytes of data can be accessed continuously in one access. FIG. 4 differs from FIG. 3 in that the direction of data flow is reversed, and is otherwise similar to FIG. 3, so a description thereof will be omitted.

Note that the above reading and writing can be performed not only to the data register but also to the memory.

As a result of a comparative experiment of 4MB data transfer between the above method and the conventional method, this method reduced the overall processing time by 20%.
It turns out that it can be made shorter.

In the conventional method, the transfer speed between the MPU and the SPC is slower than the transfer speed between the SPC and the hard disk.
In this method, the transfer speed between the MPU and the 820 is higher than the transfer speed between the SPC and the hard disk, so the
Considering the transfer speed between the U and the hard disk, in the case of this method, the transfer speed between the SPC and the hard disk is meaningful, and in the case of the conventional method, the transfer speed between the MPU and the 820 is meaningful. . When comparing the overall processing time, processing time other than pure data transfer in the program is also effective. Therefore, when we compared the data transfer time between the MPU and 820 in both methods, we found that this method was about half as fast as the conventional method.

<Effects of the Invention> As is clear from the above, according to the data transfer method between the microprocessor and the FIFO buffer of the present invention, the address of the FIFO buffer is Mapping is done in a way that ignores 2 bits, and the microprocessor and FI
By accessing the FIFO buffer with a data size that is greater than the data bus width between the FO buffers, the microprocessor's bus sizing function works, and in one access, the access size is as much as the number of bits of data that corresponds to the data bus width. Since data is transferred continuously a predetermined number of times depending on the data, there is no need for special hardware such as DMA.
Data can be transferred much faster than conventional byte access methods.

Furthermore, the data transfer method between the microprocessor and the FIFO buffer of the present invention can be used to convert software byte accesses to longword accesses even if a conventional device using an MPU with a bus sizing function already exists. In terms of hardware, this can be easily achieved by simply changing the address bus connection.

[Brief explanation of drawings]

Figure 1 is a diagram explaining the bus sizing for 32-, 16-, and 8-bit ports when an instruction that requires reading a longword operand is executed, and Figure 2 shows the data transfer method of this invention. A block diagram of one embodiment, FIG. 3 is an FI using the data transfer method of the present invention.
Diagram 4 explaining the state of reading from the FO buffer
The figure is a diagram illustrating the state of writing to the FIFO buffer. 201...Microprocessor, 202...Small computer system interface protocol controller, 203...Hard disk, 2o4...Address bus, 205...Data bus.

Claims (1)

[Claims] (1) Microprocessor capable of bus sizing is F
A data transfer method between a microprocessor and a FIFO buffer when transferring data to other devices via an IFO buffer, in which the lower 2 bits of the address are ignored in the address that is a multiple of 4 of the microprocessor. Mapping the FIFO buffer in the form of
FI with a data size greater than the data bus width between buffers
A data transfer method between a microprocessor and a FIFO buffer, characterized in that the bus sizing function of the microprocessor is used by accessing the FO buffer.