JPS6226728B2 - - Google Patents

Description

Detailed Description of the Invention [Technical Field of the Invention] The present invention relates to a microprogram-controlled computer in which all memory access control when executing a move (MOVE) instruction is performed by a microprogram. This is to prevent unnecessary operations.

[Conventional technology and problems]

In conventional microprogram-controlled computers, when executing the MOVE instruction at high speed, a memory access control circuit is provided, and the microprogram activates the memory access control circuit.
A MOVE command was issued. However, this type of conventional method requires a large amount of hardware, and since the microprogram is not notified of completion from the memory access control circuit, the actual memory
It required more time than the access time.

[Purpose of the invention]

The present invention is based on the above considerations, and includes:
Reduces the amount of hardware and improves efficiency
The purpose of this invention is to provide a movement control method that can execute MOVE commands.

[Structure of the invention]

Therefore, the movement control method of the present invention includes, in a computer controlled by a microprogram, a read align circuit that aligns data read from the main memory, and 2 that stores aligned data from the read align circuit. a selector that outputs the contents of one of the two data registers in response to a control signal, a write align circuit that aligns the output of the selector, and a read align circuit for the read align circuit. A read alignment amount designation circuit that specifies the read alignment amount, a write alignment amount designation circuit that specifies the write alignment amount for the above write alignment circuit, and a length that holds the remaining write data amount in the process of executing a move instruction.・A register, a second operand address register that specifies the main memory read address when executing a move instruction, and a first operand address that specifies the main memory write address when executing a move instruction.・A register, a comparison circuit that compares the content of the length register with the amount of prefetched data determined by the read alignment specified amount of the read alignment amount specification circuit and the bus width of the main memory, and a comparison circuit for executing the move instruction. The microprogram that executes the above movement instruction refers to the output of the comparator circuit and preempts the contents of the length register when the contents of the length register become less than the bus width of the main memory. Check whether it is less than or equal to the amount, and if it is not, command to read main memory, then command write to main memory,
If the following conditions apply, the device is characterized in that it is configured to instruct writing to the main memory.

[Embodiments of the invention]

Hereinafter, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG.
This figure is a diagram for explaining the MOVE instruction, and FIG. 3 is a diagram showing part of a microprogram for executing the MOVE instruction in the present invention.

In Figure 1, 1 is the main memory, 2 is the read memory
Align circuit, 3 is write align circuit, 4-
A and 4-B are registers, 5 is a selector, 6 is a control circuit, 7 is a first operand address register, 8 is a second operand address register,
9 is a length register, 10 is an 8-byte address register, 11 is a read alignment amount designation circuit, 12 is a write alignment amount designation circuit, 13
indicate the comparison circuits, respectively.

The main memory 1 has a bus width of 8 bytes. The read alignment circuit 2 round-shifts the data read from the main memory 1 by a specified read alignment amount. The output of read align circuit 2 is first sent to register 4-
Written to A, 4-B. The selector 5 outputs the contents of the register 4-A or 4-B in response to a control signal. The write align circuit 3 is
The output of the selector 5 is round-shifted by the specified write alignment amount. The output of the write align circuit 3 is sent to the main memory 1. The control circuit 6 includes a read alignment amount designation circuit 11, a write alignment amount designation circuit 12, and a comparison circuit 13.
have. The comparison circuit 13 compares the content of the length register 9 with the amount of prefetched data determined by the content of the read alignment amount designation circuit 11 and the bus width of the memory, and outputs a signal when the latter is less than the former.
Turn on SA. For example, the memory bus width is 8
If the byte and read alignment amount is 6 bytes on the left, the prefetch data amount is 2 bytes. The contents of the first operand address register 7 are updated by the read amount each time the first operand is read from main memory 1, and the contents of the second operand address register are updated by the amount read each time the second operand is written to main memory 1. It is updated by the write amount each time. length·
The contents of register 9 are decremented each time the second operand is written to main memory 1 by the amount written. In the 8-byte address register 10, the 8-byte address of the first operand address register 7 or the second operand address register 8 is set. The read alignment amount is determined by the 8-byte address of the second operand address register 8, and
The amount of write alignment is determined by the address within 8 bytes of address register 7.

FIG. 2 is a diagram for explaining the MOVE command. The MOVE command is OPC is the operation code, L is the length, OP1 is the first operand address, and OP2 is the second operand address. In the example in Figure 2, the second operand address OP2 is address 4, and the first operand address OP1 is address 806.
When the MOVE instruction is executed, the data specified by the length L from address 4 onwards is moved from address 806 onwards.

Next, the present invention will be explained with reference to FIGS. 1 and 2. First, data A and B are read from the main memory 1, and the read alignment circuit 2
Byte shifted. The data shifted by 4 bytes is shifted to the right by 6 bytes by the write align circuit 3 and written to address 806 of the main memory. The contents of length register 9 are then incremented by -2, the contents of second operand register 8 are incremented by +2, and the contents of first operand address register 7 are also incremented by +2. Next, the second operand
Reads 10 bytes of data from the area specified by address register 8. Since main memory 1 is 8 bytes wide, this reading is performed in two steps. First, data at addresses 0 to 7 is stored in main memory 1.
The data at addresses 8 to 15 are then read from main memory 1, shifted 6 bytes to the left, and set in registers 4-A and 4-B. written to. At this time, data already written in register 4-A is prevented from being destroyed. Note that from now on, the read alignment amount is fixed to 6 bytes, and the write alignment amount is fixed to 0 bytes. Data C, D, ......J of register 4-A are sent to main memory 1 via selector 5, and are stored in main memory 1.
8 bytes are written starting from address 808. Then, the contents of length register 9 are incremented by -8, and the contents of second operand address register 8 are +
10, first operand address register 7
The content of is increased by +8. At this stage, the read data are A, B...L, and the written data are A, B,...J. As you can see, 2 bytes of data are prefetched. Next, data at addresses 16 to 23 are read from main memory 1, shifted 6 bytes to the left, and written to registers 4-A and 4-B. At this time, the first two bytes of the data already written in register 4-B are prevented from being destroyed. Data K, L, . . . R of register 4-B is sent to main memory 1 via selector 5 and write align circuit 3, and 8 bytes are written to address 816 onwards in main memory 1. Thereafter, similar processing is repeated. When the content of length register 9 is less than 8 bytes, it is checked whether signal SA is on, and if signal SA is on, register 4-A
Or, all or part of the prefetch data existing in 4-B is written to main memory 1, and signal SA is
When it is OFF, data is read 8 bytes from main memory 1, shifted 6 bytes to the left, written to registers 4-A and 4-B as described above, and written to registers 4-A and 4-B. - All or part of the data of B is written to the main memory 1.

FIG. 3 shows part of a microprogram for executing the MOVE instruction in the present invention. In addition, in FIG. 3, MS means main memory. The microprogram performs the following processing.

Perform MS read.

Do MS Lite.

Check whether the contents of the length register are less than 8 bytes. If Yes, perform the process, and if No, perform the process.

Check whether signal SA is on or off. When it is on, the process is performed, and when it is off, the process is performed.

Perform MS read.

Do MS Lite.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, a MOVE instruction can be efficiently executed with a small amount of hardware.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG.
This figure is a diagram for explaining the MOVE instruction, and FIG. 3 is a diagram showing part of a microprogram for executing the MOVE instruction in the present invention. 1...Main memory, 2...Read align circuit, 3...Write align circuit, 4-A and 4-
B...Register, 5...Selector, 6...Control circuit, 7...First operand address register, 8...Second operand address register, 9...Length register, 10...8 bytes Internal address register, 11...Read alignment amount designation circuit, 12...Write alignment amount designation circuit, 13...Comparison circuit.

Claims (1)

[Claims] 1. In a computer controlled by a microprogram, a read align circuit aligns data read from the main memory, and two data processors store aligned data from the read align circuit. a register, a selector that outputs the contents of one of the two data registers in response to a control signal, a write align circuit that aligns the output of the selector, and a read alignment amount for the read align circuit. a read alignment amount designation circuit that specifies the write alignment amount for the write alignment circuit; a length register that holds the remaining write data amount in the process of executing the move instruction; a second operand address register that specifies a main memory read address when executing a move instruction; a first operand address register that specifies a main memory write address when executing a move instruction; A comparison circuit that compares the amount of prefetched data determined by the read alignment amount specified by the read alignment amount specification circuit and the bus width of the main memory with the content of the length register, and a microprogram for executing a move instruction. When the content of the length register becomes less than the bus width of the main memory, the microprogram that executes the above movement instruction refers to the output of the comparison circuit and determines whether the content of the length register is less than the prefetch amount. Checks whether or not, and if it is not less than, commands to read main memory, then commands write to main memory,
A movement control method characterized in that the movement control method is configured to issue a write instruction to a main memory if: