JPH0241771B2 - - Google Patents

Description

[Detailed description of the invention]

[Industrial Application Field] The present invention has object code compatibility with existing microprocessors, and is useful in systems using microprocessors that differ in the way return addresses for interrupt processing are generated. The present invention relates to an information processing device for solving the problem of sexual problems. [Prior Art] Conventionally, there have been microprocessors that are compatible with existing microprocessors in terms of object code, but have different methods of generating return addresses in the same interrupt processing. [Problems to be Solved by the Invention] However, there is a problem in that the same software causes different operations in each microprocessor due to differences in the method of generating return addresses for interrupt processing. SUMMARY OF THE INVENTION In order to solve these conventional problems, it is an object of the present invention to allow each microprocessor to perform the same operation even if an interrupt occurs with a different return address generation method. [Means for Solving the Problem] The present invention includes a detection means for detecting a predetermined interrupt processing, and a return from the interrupt processing that is stored in a first predetermined area of a memory according to the result from the detection means. Return address modification means is activated by return address modification processing activation information for activating address modification processing and executes the return address modification processing; and for activating the interrupt processing from the first predetermined area of the memory to be accessed. memory switching means for switching to a second predetermined area for storing interrupt processing activation information, and when a predetermined interrupt processing is detected, a process for correcting a return address from the interrupt processing and a process for executing the predetermined interrupt processing. It is characterized by [Operation] By adding the device configured as above to a computer, if the start address of the return address correction routine is written in the separate memory mentioned above, the value referenced by the microprocessor will be available when the desired interrupt occurs. can be the beginning of a processing routine. Modify the return address within the processing routine so that it is equal to the return address generated by the same interrupt in the existing microprocessor. By reading another memory, the start address of the original interrupt processing routine can be obtained, so by transferring control there, it is possible to obtain the same operation as a system using an existing microprocessor. can. [Example] First, the principle of the present invention will be explained using FIGS. 1 and 2. First, FIG. 1 will be explained. In the present invention, when a certain value (for example, 01H) is written in area 10 (data flow 113), in order to read out the 01H,
The CPU accesses area 11. (Data flow 114) Then, the read access to area 11 is converted and actually accesses area 10. Further, when a certain value (for example, 02H) is written in area 11 (data flow 116), the CPU accesses area 10 in order to read out the 02H.
(Data flow 115) Then, in the same way as above, access to area 10 is actually accessed to area 11.
02H is read. Here, first, before the predetermined interrupt processing is detected, the CPU writes information for starting the predetermined interrupt processing (for example, the start address of the program that executes the interrupt processing) to the area 10, Information for activating return address modification processing from the interrupt processing (for example, the start address of a program for return address modification processing) is written in area 11. Therefore, when the specified interrupt processing is detected,
When the CPU makes read access to area 10, information for starting the return address correction process in area 11 is actually read, and the return address correction is executed first before interrupt processing. Furthermore, unlike FIG. 1, FIG. 2 shows a case where areas 10 and 11 are interchanged in the write operation. That is, in the case of FIG. 2, in the case of reading, data (data flows 224, 225) can be read from the area designated by the CPU. However, in the case of writing, when area 10 is specified by the CPU, it is actually written to area 11, and when area 11 is specified (data flow 223), it is actually written to area 10. (Data flow 226)
In the case of Fig. 2, the CPU performs write access to area 10 before the predetermined interrupt processing occurs, and actually writes information to start the interrupt processing in area 11, and ,
The CPU performs write access to area 11 and actually writes information in area 10 to start the return address correction process.
Then, when a predetermined interrupt process is detected, area 10 is accessed, and as in FIG.
Return address correction processing is executed. Examples of the present invention are shown below. FIG. 3 is an embodiment of a memory control circuit for implementing the present invention. In FIG. 3, 1 is a special interrupt vector address code circuit, and when the address of the special interrupt vector is selected, the signal 35 is set to 0.
is output, and when another address is selected,
Outputs 1. 2 is a memory select circuit, which determines the BANK signal 30 based on a select signal (not shown) from software. A special interrupt vector is an interrupt vector for an interrupt in which the return address from interrupt processing is generated differently from existing microprocessors. FIG. 4 shows a memory map. In this figure, memory 20 is a special interrupt vector, and memory 21 is another memory that corresponds to memory 20 and has no operational problems. Also, MRN is a memory read signal, MWN is a memory write signal, and 0 is a
a memory read signal for the main memory 25;
MR1 is a memory read signal for the memory 21, MR1 is a memory write signal for the main memory 25, and 1 is a memory write signal for the memory 21. In this circuit, when the BANK signal 30 is 0, the signal 31 is equal to 1, and the signal 36 is equal to the signal 35. When the signal 35 is 0, the gate 42 and the gate 43 are open, and when the signal 35 is 1, the gate 41 and the gate 43 are open. gate 4
3 opens. Also, when the BANK signal 30 is 1, the signal 36 is 1, the signal 31 is equal to the signal 35,
When the signal 35 is 0, the gates 41 and 44 are open, and when the signal 35 is 1, the gates 41 and 43 are open. As a result, when the special interrupt vector is selected, if the BANK signal 30 is 0,
If memory 21 can be read and written to memory 20 and BANK signal 30 is 1, memory 20 can be read and written to memory 21. Further, when a special interrupt vector is not selected, reading and writing are performed to the main memory 25. An existing processor is referred to as processor 0, and a processor that is compatible with processor 0 in terms of object code and that generates a return address from interrupt processing in a different manner is referred to as processor 1. In FIG. 5, in processor 0, instruction 51
When a special interrupt occurs, the return address from the processing is the next instruction 52, and the processor 1 returns the special interrupt that occurred at the instruction 51. Suppose there is. In this case, processor 1 will loop at instruction 51, resulting in a completely different operation from processor 0. Therefore, the interrupt vector of the interrupt that occurred at instruction 51 is changed to vector 53 in the return address processing routine. If you modify the return address from interrupt processing to instruction 52 in the return address processing routine and move the processing to the original interrupt processing routine (arrow 54), the return address after processing will become instruction 52. Therefore, processor 0 and processor 2
appears to have the same behavior. Therefore,
In a system using this circuit, at startup
The BANK signal 35 is set to 1, the start address of the return address correction routine is written in the memory 21, and the BANK signal 35 is set to 0. (100) By doing this, for the special interrupt vector, when reading, the start address of the return address correction routine is read, and when writing, data is written to the memory 20. Then, an application program or the like is executed. (101) When a special interrupt occurs during execution, the special interrupt vector is referenced, but the memory 21 is read at this time, (102)
Since it points to the start address of the return address modification routine, control is transferred to the return address modification routine instead of the special interrupt handling routine. (103) In the return address correction routine, the return addresses are rewritten so that they are equal, and the BANK signal 35 is set to 1.
and read out the memory 20. This makes it possible to obtain the original start address of the interrupt process. Then, the BANK signal is set to 0 (104) and control is transferred to the original interrupt handling routine. (106) This makes it possible to perform apparently the same operation. That is, incompatibilities due to differences in the method of generating return addresses from interrupt processing are resolved. Next, the case of 80286CPU and 8086CPU will be explained as a specific example. The 80286CPU is a microprocessor that is compatible with the 8086CPU in terms of object code, but differs in the way return addresses are generated for divide-by-zero interrupt processing. Therefore, when a divide-by-0 interrupt occurs, incompatibility occurs due to differences in the interrupt processing and return address. In order to eliminate this incompatibility, a circuit as shown in FIG. 7 is used. This circuit uses address bus AB
When all of 2 to AB23 are 0, 0 is output to the signal 35, and 1 is output to the signal 35 at other times. The divide-by-zero interrupt vector is the memory address
Since it is stored in 0H to 3H, when a divide by 0 interrupt vector is selected, 0 is output to signal 35, and when any other address is selected,
1 is output to signal 35. Also, in the memory select circuit, the address bus
AB0 to AB3 are all 1, address bus AB4
~When AB7 is all 0, the signal changes from 0 to 1
DB0 is output as BANK signal 30 when
When outputting 1 to O port OFH, BANK signal 30
1 is output. The memory map at this time is
As shown in the figure. Figure 8 shows the memory map at this time. In this figure, memory 61 is the main memory of the 80286 CPU,
The memory 62 is a memory on the main memory 61 where the divide-by-zero interrupt vector is written, and the memory 63
is a bank memory that corresponds to the memory 61 and has no operational problems. Also, in Figure 7,
is a memory read signal for the main memory 61, and 1 is a memory read signal for the bank memory 63.
A read signal is a memory write signal for the main memory 61, and 1 is a memory write signal for the bank memory 63. As mentioned above, in the circuit of FIG. 7, when the divide-by-0 interrupt vector is selected, the BANK signal 30
When is 0, the contents of the bank memory 63 are read for a memory read, and written to the 0-divide interrupt vector 62 of the main memory 61 for a memory write. Furthermore, when the BANK signal 30 is 1, the contents of the divide-by-zero interrupt vector 62 of the main memory 61 are read for memory read, and written to the bank memory 63 for memory write. If BX = 0 in the instructions DIV DX, BX, both the 80286CPU and 8086CPU will generate a divide-by-zero interrupt, but the return address from the processing routine for the 80286CPU will point to the instruction that caused the interrupt. However, on the 8086 CPU, it points to the instruction following the instruction that caused the interrupt. If BX=
If the interrupt processing routine returns with the value 0, the 80286 CPU will generate a divide-by-0 interrupt again and the program will stop. However, with the 8086CPU, there is an incompatibility in that the processing moves to the next instruction after the instruction that caused the interrupt, and the subsequent processing continues. Therefore, when a divide-by-zero interrupt occurs, the 80286 CPU reads the divide-by-zero interrupt vector and transfers control to the address indicated by that vector.
If you output 0 to , the 80286 CPU will read 0.
The division interrupt vector can be a value in bank memory 63. Next, an example of a return address modification routine will be explained. A list of this routine is shown in Table 1. When an interrupt is received, this return address modification routine first secures a 4-byte stack area for branching to the division-by-zero interrupt processing routine of the application program. (201) Next, each register is saved. (202) Since the start address of the instruction that caused the error is the return address for interrupt processing, that address is stored in the DS register for the segment and the SIL register for the offset. (203) Then, the prefix part of the instruction code is skipped. (204) The prefix part is 001××110b in binary code, so only this part is skipped. (205) Next, check whether the instruction that caused the interrupt is a division instruction. In this case, the divide by 0 instruction is
The binary code is 00×××110b, so check if the instruction that caused the interrupt is like this. (206) If it is not a 0-divide instruction, for example a 1NTO instruction, control is passed to the application's interrupt handling routine without modifying the return address. (207) If it is a division instruction, find the instruction length. First, look at the second byte of the instruction and see that the code is a binary code, 00×××
If it is 110b, it is a memory operand instruction, so in this case, it is a 4-byte instruction, if the 7th and 6th bits are 11 or 00, it is a 2-byte instruction, and if the 7th and 6th bits are 01, it is a 3-byte instruction. 7th and 6th bits
Since 10 is a 4-byte instruction, this allows us to know the beginning of the instruction following the instruction that caused the interrupt. (208) If this is written in the area where the return address is written, (209) the return address will be corrected. Then, the application 0 written in the division interrupt vector 62 of the main memory 62
Write the start address of the division interrupt processing routine to the stack area reserved for branching. (210) Then, by restoring the register (211) and executing a return instruction, processing can be transferred to the application's division-by-zero interrupt processing routine. And the return address from that routine is
This becomes the next instruction after the instruction that caused the divide-by-0 interrupt, allowing the 80286 CPU to operate in the same way as the 8086 CPU. In the examples explained so far, bank memory was used as the separate memory, but the separate memory can be any type of memory, such as I/O memory or memory on main memory that does not cause problems in system operation. may also be used.

【table】

[Table] Also, for the 80286CPU, regarding interrupts that the 8086CPU does not have, such as segment overrun error interrupts, this interrupt is
Beyond the segment, such that = OFFFFH,
This is an interrupt that occurs in the 80286 CPU when attempting to access memory. This interrupt is
This does not occur on 8086 CPU. Therefore, in this case as well, the present invention is used to perform the same processing as the 8086CPU in the return address correction routine, and by setting the return address next to the instruction that caused the interrupt and returning, the 80286CPU can
It becomes possible to perform operations similar to those described above, and this incompatibility caused by interrupts can be resolved by using the present invention. [Effects of the Invention] As described in detail above, the present invention is configured such that when the detection means detects a predetermined interrupt process, the return address correction means is activated to correct the return address of the predetermined interrupt process. (a) Compatibility between processors with different interrupt handling can be achieved. Therefore, software for processor A, which conventionally did not work due to differences in interrupt processing, now works on processor B, greatly improving usability for the user. (b) In the past, in order to run a large number of software, multiple processors were required due to the incompatibility between processors, but according to the present invention, only one processor is required, and the device Simplification, low cost, and savings in mounting space can be achieved. (c) For example, if there is a processor C with a fast operating speed and a processor D with a slow operating speed, by using the present invention to execute software for processor D on processor C, the software can be executed faster than before. It has the great advantage of being able to

[Brief explanation of the drawing]

1 and 2 are operational conceptual diagrams of the memory read/write control circuit. FIG. 3 is a circuit diagram showing an example of a circuit implementing the present invention. FIG. 4 is a diagram showing a memory map at that time. FIG. 5 is an operational diagram of interrupt operation. FIG. 6 is a flowchart of the above embodiment. FIG. 7 is a specific circuit diagram for implementing the present invention. FIG. 8 is a diagram showing a memory map at that time. FIG. 9 is a diagram showing a timing chart of the circuit of FIG. 7. 113...Data flow when writing to the special interrupt vector, 114...Data flow when reading from the special interrupt vector, 115...Data flow when reading from another memory, 116...To another memory Data flow when writing.

Claims (1)

[Claims] 1. Detection means for detecting predetermined interrupt processing;
In response to the result from the detection means, the return address modification processing is activated by return address modification processing activation information for activating the return address modification processing from the interrupt processing, which is stored in a first predetermined area of the memory. return address modification means for executing the return address; and memory switching means for switching the memory to be accessed from the first predetermined area to a second predetermined area storing interrupt processing activation information for activating the interrupt processing, An information processing apparatus characterized in that, when an interrupt process is detected, a process of correcting a return address from the interrupt process and the predetermined interrupt process are executed.