JPS63233438A - Memory controller - Google Patents

Abstract

PURPOSE:To eliminate non-interchangeability between processors different in return address generating method by providing the titled device with a circuit for controlling the reading/writing operation of a memory. CONSTITUTION:A memory 20 corresponds to a specific interruption vector in a main memory 25 and a memory 21 corresponds to the memory 20. A specific interruption vector address decoder 1 outputs a '0' signal to a signal line 35 when a specific interruption vector address is selected, and in other cases, outputs an '1' signal. A memory selecting circuit 2 outputs a BANK signal 30 on the basis of a SELECT signal. If the BANK signal is '0' when the specific interruption vector is selected, the contents of the memory 20 are read out and the memory 20 becomes writable. When the BANK signal is '1', the contents of the memory 20 are read out and the memory 21 becomes writable. When the specific interruption vector is not selected, data are read out/written from/in a main memory 25.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is applicable to existing microprocessors and objects.
The present invention relates to a memory control device for resolving incompatibility in a system using a microprocessor that has compatible codes but differs in the method of generating a return address for interrupt processing.

[Prior Art] Conventionally, there have been microprocessors that are compatible with existing microprocessors in terms of object code, but have different methods of generating return addresses in the same interrupt processing.

[Problem to be solved by the invention] However, due to differences in the way return addresses for interrupt processing are generated, each microprocessor has
This solved the problem of the same software performing different operations.

SUMMARY OF THE INVENTION In order to solve these conventional problems, it is an object of the present invention to allow each microprocessor to perform the same operation even if an interrupt occurs with a different return address generation method.

``Means for Solving Problem 1'': In order to solve the problem described above, in the present invention, an existing microprocessor is configured to handle the memory in which the interrupt vector is written, which has a different return address generation method for interrupt processing. As shown in Figure 1, when writing, data is written to the memory (data flow 3.6), and when reading, the memory is switched and the other memory is read (data flow 3.6). Flow 4, 5.) When writing, switch the memory and write to another memory as shown in Figure 2, and when reading, use a circuit that has the function to read that memory and control that circuit. and a program that has the function of modifying the return address,
It is characterized by having the following.

[Operation] By adding the device configured as described above to a computer, if the start address of the return address correction routine is written in the separate memory mentioned above, the value referenced by the microprocessor can be set when the desired interrupt occurs. ,
Can be placed at the beginning of a processing routine. Modify the return address in the processing routine so that it is equal to the return address generated by the same interrupt in the existing microprocessor. By reading another memory, the start address of the original interrupt processing routine can be obtained, so by transferring control there, it is possible to obtain the same operation as a system using an existing microprocessor. .

[Embodiment] An embodiment of the present invention will be shown below. FIG. 3 is an embodiment of a memory control circuit for realizing the present invention. In FIG. 3, l is a special interrupt vector address lever 1 circuit, which outputs O to the signal 35 when the address of the special interrupt vector is selected, and outputs 1 to the signal 35 when any other address is selected. Output. 2 is a memory select circuit, which receives a select signal (not shown) from software.
Accordingly, the BANK signal 30 is determined. A special interrupt vector is an interrupt vector for an interrupt in which the method of generating a return address from interrupt processing is different from existing microprocessors.

FIG. 4 shows a memory map. In this diagram, memory 20
is a special interrupt vector, and memory 21 is another memory that corresponds to memory 20 and has no operational problems. Also, MR
N is a memory read signal.

MWN is a memory write signal, MRO is a memory read signal for the main memory 25, MRl is a memory read signal for the memory 21, MWO is a memory write signal for the main memory 25, and MWI is a memory write signal for the memory 21. It's a signal.

In this circuit, when the BANK signal 30 is 0, the signal 31 is 1, the signal 36 is equal to the signal 35, when the signal 35 is 0, the gate 42 and the gate 43 listen, and when the signal 35 is 1, the gate 42 and the gate 43 listen. ) 41 and gate 43 are open, and BANK signal 35 is 1, signal 36 is 1, and signal 31 is 35.
and when the signal is 0, gate 41 and gate 4
4 is open and signal 35 is 1, gate 41 and gate 4
3 is open, so that when the special interrupt vector is selected, if the BANK signal 30 is 0, the memory 21 can be read and written to the memory 20, and the BANK
If signal 30 is 1, memory 20 can be read and memory 21 can be written. Also, when a special interrupt vector is not selected, reading and writing are performed using the main memory 25.
It is done for.

Processor 0. processor O;
Processors that are compatible in object code and differ in the ability to generate return addresses from interrupt processing,
Let the processor be l.

In FIG. 5, in processor 0, when a special interrupt d occurs at instruction 51, the return address from that processing is the next instruction 52, and processor l handles the special interrupt that occurred at instruction 51. Assume that the return address from processing is instruction 51.

In this case, processor 1 would end up in a loop at instruction 51, resulting in a completely different operation from processor O.Therefore, the interrupt vector for the interrupt that occurred at instruction 51 would be set to the return address processing routine like vector 53. Then, in the return address processing routine, if you modify the return address from interrupt processing 1 to instruction 52 and move the processing to the original interrupt processing routine 1 (arrow 54), the return address after processing will be instruction 52. , processor 0 and processor 2 apparently perform the same operation. Therefore, in a system using this circuit, the BANK signal 35 is set to 1 at startup, the start address of the return address correction routine is written in the memory 21, and the BAMK signal 35 is set to 1.
Set to 0. (100) By doing this, for the special interrupt vector, when reading, the start address of the return address correction routine is read, and when writing, data is written to the memory 20.

Then, an application program or the like is executed.

(101) When a special interrupt occurs during execution, the special interrupt vector is referred to, but what is read at this time is the memory 21, and (102) it points to the start address of the return address correction routine, so Control is transferred to the return address modification routine rather than the special interrupt handling routine. (103) In the return address correction routine, the return addresses are rewritten so that they are equal, the BANK signal 35 is set to 1, and the memory 20 is read. This changes the original start address of the interrupt processing. Obtainable. Then, the BANK signal is set to O, (104) control is transferred to the original interrupt handling routine, (106), and this makes it possible to apparently perform the same operation. That is, incompatibilities due to differences in the method of generating return addresses from interrupt processing are resolved.

Next, the case of 80286 CPU and 80860 PU will be explained as a specific example. 80286 CPU is 8086CP
It is a microprocessor that is compatible with U in terms of object code, but the method of generating the return address for divide-by-zero interrupt processing is different.

Therefore, when a divide-by-0 interrupt occurs, incompatibility occurs due to differences in the interrupt processing and return address.

In order to eliminate this incompatibility, a circuit as shown in FIG. 7 is used. This circuit outputs 0 to signal 35 when address buses AB2 to AB23 are all O, and outputs 1 to signal 35 at other times.

The division by 0 interrupt vector is the memory address OH-3H.
Therefore, when the 0-divided interrupt vector is selected, O is output to the signal 35, and when any other address is selected, 1 is output to the signal 35.

In addition, in the memory select circuit, the address bus ABON
DBO when AB3 is all 1, address buses AB4 to AB7 are all 0, and the IOW signal changes from 0 to 1.
is output as the BANK signal 30, that is, when 0 is output to the I10 port OFH, O is output to the BANK signal 30, and the I10 port OFH
When the BANK signal 30 is outputted, 1 is outputted to the BANK signal 30. The memory map at this time is shown in FIG.

FIG. 8 shows the memory map at this time. In this figure, memory 61 is the main memory of the 80286CPtl, memory 62 is the memory on the main memory 61 where the divide-by-zero interrupt vector is written, and newt 63 is the memory 61. It is a compatible bank memory with no operational problems. Also, the seventh
In the figure, MW) is a memory read signal for the main memory 61, MHI is a memory read signal for the bank memory 63, MWO is a memory write signal for the main memory 61, and MWI is a memory write signal for the bank memory 63. It's a signal.

As mentioned above, in the circuit of FIG. 7, when the divide-by-0 interrupt vector is selected and the BANK signal 30 is O, the contents of the bank memory 63 are read out for memory read, and the contents of the bank memory 63 are read out for memory write. Regarding main memory 6
To the O division side of 1/y )) 62 D book,! When BAN K4B@3.30 is 1, there is no memory read.

The contents of the O division side input vector 62 of the bank memory 61 are read out, and regarding the memory line I, the contents of the bank memory 6
Written in 3. If BX=0 in the command DIV DX, BX, then 80
Both the 286 CPU and 8086 CPU generate O division side interrupts, but the return address from the processing routine for the 80286 CPU points to the instruction that caused the interrupt, but for the 80860 PU it points to the next instruction after the instruction that caused the interrupt. ing. If the interrupt handling routine returns with BX = 0, 802860 PU
In this case, a divide-by-zero interrupt is generated again and the program stops.However, in the 8086 CPU, processing has moved on to the next instruction after the instruction that caused the interrupt, so the subsequent processing continues. Compatibility has occurred. Therefore, when a divide-by-0 interrupt occurs, the 80286 CPU reads the divide-by-O side interrupt vector and transfers control to the address indicated by that vector.
If 0 is output to the I10 baud 1-OF H at the time of system boot, the O division side input vector read by the 80286 CPU can be set to the value of the bank memory 63.

Next, an example of the return at 1/s repair iE routine will be explained. A list of this routine is shown in Table PI3.

When an interrupt occurs, this return address modification routine first creates a stack area of 4 for branching to the application program's divide-by-zero interrupt handling routine.
Secure a part-time job. (201) Next, save each register. (202) Then, since the start address of the instruction that caused the error is the return address of 1 interrupt processing, that address is stored in the DS register as a segment. The offset is placed in the SIL register. (2
03) Then, skip the prefix part of the instruction code. (204) Since the bfix part is 0O1xxllOb in binary code, only this part is skipped. (205) Next, it is checked whether the instruction that caused the interrupt is a division instruction. In this case, the divide-by-zero instruction has a binary code of 00xxxllOb, so it is checked whether the instruction that caused the interrupt is like this. (206) If it is not an O division instruction, for example an INTO instruction, control is passed to the interrupt processing routine of the application without modifying the return address. (207) If it is a division instruction, the instruction length is seek. First, look at the second byte of the instruction and see if the code is 2.
If the hex code is 00xxxllOb, it is a memory operand instruction, so in this case, it is a 4-byte instruction.

7. If the 6th bit is 11 or 00, a 2-byte instruction,
7.6-bit I/If the eye is 01, it is a 3-byte instruction.

7. If the 6th bit is 10, it is a 4-byte instruction, so this indicates the beginning of the instruction following the instruction that caused the interrupt. (20B) If this is written in the area where the return address has been written (209), the return address has been corrected.

Then, the divide-by-zero interrupt vector 62 in the main memory 62
Writes the start address of the application's divide-by-zero interrupt processing routine written in the stack area into the area reserved for branching (210).Then, when the register is restored and the return instruction is executed (211), the divide-by-0 side of the application processing can be transferred to the import processing routine.

The return address from that routine is the next instruction after the instruction that caused the divide-by-zero interrupt.80286C
It becomes possible to operate the PU in a manner similar to that of the 8086 CPU.

In the example explained so far, an example was shown in which bank memory was used as the separate memory.
Any memory may be used, such as 0 memory, memory on the main memory that does not cause any problem in system operation.

X Bu A Deep A --Φ A
, Ω1 A Also, regarding an interrupt that exists in the 80286 CPU but not in the 8086 CPU, for example, a segment overrun error interrupt, this interrupt is MOV AX:
[BX] In a memory access instruction such as
This is an interrupt that occurs in the 80286 CPU when an attempt is made to access memory beyond a segment that results in FFFH. This interrupt does not occur in the 8086 CPU, so in this case as well, the present invention is used to perform the same processing as in the 80860 PU in the return address correction routine, set the return address next to the instruction that caused the interrupt, and then return. Niri, 80286CP
It becomes possible to operate the CPU in a manner similar to that of the 8086 CPU, and this incompatibility due to interrupts can be resolved by using the present invention.

[Effects of the Invention] As explained above, the present invention adds a memory read/write operation control circuit and a program that controls the circuit and corrects the return address, thereby improving the efficiency of existing microprocessors. , in a system using microprocessors with compatible object codes, it is possible to eliminate incompatibilities caused by different methods of generating return addresses for the same interrupt processing.

[Brief explanation of the drawing]

1 and 2 are operational conceptual diagrams of a memory read/write control circuit, FIG. 3 is a circuit diagram showing an example of a circuit implementing the present invention, and FIG. 4 is a diagram showing a memory map at that time. , FIG. 5 is an operational diagram of the interrupt operation, and FIG. WS6 is a flowchart of the above embodiment. Figure ff57 is a specific circuit diagram for implementing the present invention. ff FIG. 18 is a diagram showing a memory map at that time, and FIG. 9 is a diagram showing a timing chart of the circuit of FIG. 7. 3... Data flow when writing to the special interrupt vector 4... Data flow when reading from the special interrupt vector 5... Data flow when reading from another memory 6...
・Flow of data when writing to another memory Applicant Seiko Even Co., Ltd. Figure 1 Figure 2 Figure 3 Figure 4 Figure 6 Figure 7 Figure 8

Claims (1)

[Claims] In a system that uses a microprocessor that is compatible with existing microprocessors in object code and has a different method of generating return addresses for interrupt processing, it has a circuit that controls memory read/write operations and a return address correction program. A memory control device characterized by: