JPS62111343A - Channel control circuit - Google Patents

Abstract

PURPOSE:To attain rapid data transfer by using a direct memory access (DMA) controller, and transferring data to a data register word by word without using a program. CONSTITUTION:Data inputted from an external interface circuit 3 are stored in a large capacity internal memory 2 every input. To output data asynchronously to an external I/O device 12, the idle state of a rapid memory 7 is checked, the DMA controller 10 is started and then data are written from the internal memory 2 to the data register 8 word by word. The data are outputted to a data bus for a rapid memory 7. The initial value of a counter 6 is '0' and the value is counted up in accordance with the writing of data in the memory 7. The DMA controller 10 reads out the succeeding data from the internal memory 2 and said operation is repeated by the prescribed number of times. During the repeat of the operation, a program in an internal CPU 1 is not surely used.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a channel control device that performs high-speed data transfer in an input/output device or a node device of a local area network (hereinafter referred to as LAN). (Prior Art) FIG. 2 is a block diagram of a conventional channel control circuit. In the figure, 21 is a CPU, 22 is a ROM, 23 is an external interface, and 24 is a DMA controller, all of which are connected to a CPU bus 25. 26
27 is a bus switching circuit, and a shared memory constitutes a channel control circuit 28. This is connected to an external input/output device 29.

Data imported via the external interface 23 is transferred to the shared memory 2 by controlling the bus switching circuit 26.
7. The external input/output device 29 then retrieves this data.

In this way, data transfer was possible even in the conventional channel control circuit.

(Problems to be Solved by the Invention) With the channel control circuit configured as described above, it is difficult to satisfy all of the requirements for faster operation, larger capacity, and lower cost of the shared memory.

SUMMARY OF THE INVENTION An object of the present invention is to provide a channel control circuit that eliminates the drawbacks of the prior art and can realize high-speed data transfer, large memory capacity, and low cost.

(Means for Solving the Problems) The channel control circuit of the present invention provides
In the circuit configuration for transferring data inside the CPU at high speed, there is a memory for temporarily storing data and an internal CPU.
a bus switching circuit for controlling access contention for the shared memory between a PU and an external input/output device;
Controls bus switching according to instructions from the internal CPU,
A control circuit that resets a counter, writes the number of data to the memory, and adds the counter; and a data register that temporarily stores data output from the internal CPU and outputs this data on a data bus to the memory. and,
a counter that adds a held count value in response to a signal from the control circuit, addresses and outputs the count value on the address bus to the memory; and
The address of the internal memory where the transfer data is stored and the number of data are set by PtJ, and the data on the internal memory is output word by word to the data register by direct DMA, data matching the number of data is output, and the operation starts. The DMA controller transfers data from the memory of the internal CPU to the memory, and after the transfer is completed, the control circuit switches the memory to the external input/output device side, and from this external input/output device, This allows access to the memory.

(Function) By interfacing with the internal CPU as an I10 device, data is transferred word by word from the large-capacity internal memory to the data register by the DMA controller without program intervention, and the counter is advanced. Can be written to high-speed memory. Furthermore, when writing is completed, data can be transferred at high speed from the high speed memory to the external input/output device by switching the bus switching circuit.

(Example) An embodiment of the present invention will be described based on FIG.

FIG. 1 is a block diagram of a channel control circuit according to the present invention. In the same figure, 1 is the internal CPU, 2 is the large capacity RAM and R
Internal memory consisting of OM, 3 an external interface circuit, 4 an interrupt controller, 5 an internal CPU bus,
6 is an up counter that instructs the address to the high speed memory 7; 8 is a data register that instructs data to the high speed memory 7; 9 is a control circuit that controls bus switching and resets the counter; and 10 is an up counter that instructs the address to the high speed memory 7. A DMA controller transfers data to the high-speed memory 7, 11 is a bus switching circuit that switches the bus of the high-speed memory 7, and 12 is an external input/output device that can access the high-speed memory 7 through the bus switching circuit 11.

The data fetched from the external interface circuit 3 is stored in the large-capacity internal memory 2 each time, and when outputting data to the external input/output device 12 asynchronously, the free state of the high-speed memory 7 is checked, and the internal CPU 1
0 and writes data from the internal memory 2 to the data register 8 word by word. This data is output onto the data bus of high speed memory 7. The initial value of the counter 6 is 0, and the value is output onto the address bus of the high-speed memory 7, and as the data on the data bus is written to the high-speed memory 7, the counter is incremented, and the DMA controller:
The next data is read from the internal memory 2, and this operation is repeated a predetermined number of times.

During this time, no internal CPU program is involved. When a series of transfers is completed, an interrupt is generated, and the control circuit 9 is initialized as post-processing by the program. The counter 6 is also initialized by this initialization.

(Effects of the Invention) The present invention enables high-speed transfer between memories using DMA, increased capacity of internal memory, cost reduction due to economicalization of high-speed memory, and high-speed data transfer between high-speed memory and external input/output devices. There are various effects such as making it possible.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a channel control circuit according to an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional channel control circuit. 1...Internal CPU, 2...Internal memory, 3
... Internal interface circuit, 4 ... Interrupt controller 1 roller, 5 ... CPU bus, 6 ...
Up counter, 7...High speed memory, 8...Data register, 9...Control circuit, 10...DMA
Controller 1-Roller, 11...Bus switching circuit, 12...
・External input/output device. Patent applicant: Matsushita Electric Industrial Co., Ltd. Figure 1 Figure 2

Claims (1)

[Claims] In a circuit configuration for transferring data inside a CPU at high speed to an external input/output device, a memory for temporarily storing the data and access to the memory shared between the internal CPU and the external output device are provided. a bus switching circuit for controlling contention; a control circuit for controlling bus switching, resetting a counter, and incrementing the counter after writing data to the memory according to instructions from the internal CPU; A data register that temporarily stores data output from the internal CPU and outputs the data on the data bus to the memory, and a count value to be held by a signal from the control circuit is added, and the data is transferred to the memory. On the address bus, a counter that addresses and outputs the count value and the internal CPU set the address and number of data in the internal memory where the transfer data is stored, and direct memory access (hereinafter referred to as DMA) is performed.
a DMA controller that outputs data on the internal memory word by word to a data register and stops operation after outputting data matching the number of data, and transfers data from the memory of the CPU to the memory. After the completion of the control, the control circuit switches the memory to an external input/output device, thereby making it possible to access the memory from the external input/output device.