JPH03259491A - Memory controller - Google Patents

Abstract

PURPOSE:To improve a processing speed by implementing the execution of an access request of an input and output channel provided to a tentative storage memory in the page mode when the number of data stored in the tentative storage memory reaches the preset number of data. CONSTITUTION:A dynamic RAM (random access memory) control circuit 17 executes sequentially an access request from channels CH1-CH4 based on a preset priority. Moreover, the dynamic RAM control circuit 17 sets the data in the tentative storage memory 21 so as to access it in the page mode such as high speed page mode to the dynamic RAM 16 when a 2-word data is stored in the tentative storage memory 21 connected to a reception circuit 13 via a data bus 20. Thus, the data is transferred from the reception circuit 13 to the dynamic RAM 16 not through a microprocessor 11 and no overhead for interrupt processing takes place. Thus, the processing speed is improved.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is applicable to dynamic random printers such as laser printers.
The present invention relates to a memory control device applied to equipment using access memory.

[Prior Art] For example, a memory control device shown in FIG. 5 is used in a laser printer. This memory controller is a micro
Processor 1, ROM (read-only memory) 2, receiving circuit 3 that receives print data (codes of characters to be printed, codes for printer control, etc.) sent from the host, and data communication with other devices. Communication circuit 4
, an image data output circuit 5 that outputs image data to the printing section
, a dynamic RAM control circuit 7 that controls a dynamic RAM (random access memory) 6
It consists of In order to operate the dynamic RAM 6 normally, the dynamic RAM control circuit 7 uses RAS for address division and refreshing.
(rath signal), cAs (gas signal), WE (write enable signal), and other signal timings.

the microprocessor 1, ROM 2, receiving circuit 3,
Communication circuit 4, image data output circuit 5, dynamic RA
The M control circuits 7 are connected to each other by a system data bus 8.

The print data received by the receiving circuit 3 is always written into the dynamic RAM 6 six times, and the writing control is performed as follows.

When the receiving circuit 3 finishes reading the print data, it issues an interrupt request to the microprocessor 1.

When microprocessor 1 receives an interrupt request,
The state of the routine being executed up to that point (that is, the data stored in registers, the status of the task being executed, etc.) is saved on the dynamic RAM 6,
Control is then transferred to the interrupt handling routine. (Interrupt Pre-Processing) In the interrupt processing routine, the microprocessor 1 first reads the data received from the receiving circuit 3, then calculates the address at which the data should be stored, and writes it into the dynamic RAM 6.

When the interrupt handling routine ends, the microprocessor 1 returns the state of the previously executed routine from the dynamic RAM 6 and transfers control to that routine.

In this way, conventionally, the receiving circuit 3 is configured using the dynamic RAM 6.
The microprocessor 1 performs all data transfer between the receiving circuit 3 and the dynamic RAM 6, which performs any active operation.

Furthermore, conventionally, the dynamic RAM control circuit 7 has only one input/output channel, so only the circuit that has the right to use the system data bus 8, that is, the microprocessor 1, can access the dynamic RAM 6. Ta.

The conventional dynamic RAM control circuit 7 reads or writes one word, or both, in one cycle of access such as a read cycle, early write cycle, delayed write cycle, read modify write cycle, etc. mode) can be executed, so writing to consecutive addresses also involves repeating the single mode.

Therefore, when data X and data Y are written into the dynamic RAM 6, the timing is shown in FIG. In other words, there is a precharge time for each write of data.

FIG. 7 shows the processing of the microprocessor 1, the processing of the receiving circuit 3, and the usage status of the dynamic RAM 6 when processing A by the microprocessor 1 and receiving processing of print data X and Y by the receiving circuit 3 proceed simultaneously. It shows.

For example, assuming that processing A by the microprocessor 1 and reception of data X by the receiving circuit 3 start at the same time, the microprocessor 1 uses the dynamic RAM 6 for processing A during the 6 fixed times required to receive the data X.

When the reception of data X is completed, an interrupt request is generated from the receiving circuit 3 to the microprocessor 1. Upon receiving an interrupt request, the microprocessor 1 writes the data X received by the receiving circuit 3 into the dynamic RAM 6 by sequentially performing interrupt preprocessing, readout, write processing, and postinterrupt processing.

The receiving circuit 3 becomes operational at the same time that the microprocessor 1 finishes reading the received data X, and reads the next data Y.
Start receiving.

Further, when the reception of data Y is completed, an interrupt request is generated from the receiving circuit 3 to the microprocessor 1. However, at this point, the microprocessor 1 is still in the middle of post-interrupt processing and cannot immediately start the next interrupt processing routine.

After that, when the interrupt request is accepted, the microprocessor 1 writes the data Y received by the receiving circuit 3 into the dynamic RAM 6 by sequentially performing interrupt pre-processing, read and write processing, and post-interrupt processing.

When all interrupt processing related to received data X and Y is completed, the rest of the interrupted processing A is executed.

[Problems to be Solved by the Invention] As described above, in the conventional memory control device, the overhead of interrupt processing is large, and the processing speed is slow because the dynamic RAM is accessed only in single mode.
Additionally, there was a problem in that the waiting time before starting access was long and the processing efficiency was low.

Therefore, the present invention aims to provide a memory control device that can improve processing speed and processing efficiency.

[Means for solving the problem] The invention corresponding to claim (1) is a dynamic random
A dynamic random access circuit that has multiple input/output channels and controls access to the memory by controlling the timing of signals such as the last signal, gas signal, and write enable signal to the memory. Dynamic Random Access ◆Multiple temporary storage memories with multiple word configurations provided for all or some of the input/output channels of the memory control circuit, and one of these temporary storage memories. a microprocessor that controls the data via a system data bus and writes and reads data;
Consisting of circuit blocks that write and/or read data from the remaining temporary storage memory, the dynamic random access memory control circuit handles data from each input/output channel based on preset priorities. In addition to executing access requests sequentially, the execution of access requests for input/output channels equipped with temporary storage memory is executed in page mode when the number of data stored in the temporary storage memory reaches a preset number of data. It is something to do.

The invention corresponding to claim (2) is the invention corresponding to claim (1), when the memory control circuit during dynamic random access executes an access request for an input/output channel provided with a temporary storage memory in page mode. The number of required data in the temporary storage memory can be freely set by a microprocessor.

The invention corresponding to claim (3) is a dynamic random
The access/memory control circuit sequentially executes access requests from each input/output channel based on preset priorities, and executes access requests from input/output channels provided with temporary storage memory. When there is a plurality of data in the memory, the page mode is used, and when there is only one piece of data in the temporary storage memory, the single mode is used.

The invention corresponding to claim (4) is that in the invention corresponding to claim (3), the dynamic random access memory control circuit stores a plurality of data in the temporary storage memory, and each data is to be written. The access request is executed in page mode when the address is within the same page on the dynamic random access memory.

[Operation] In the invention according to claim (1), access requests to the dynamic random access memory control circuit from the microprocessor or circuit block are made using different input/output channels.

Data from the microprocessor or circuit block is then stored in the temporary storage memory of each corresponding channel.

The dynamic random access memory control circuit sequentially executes access requests to the dynamic random access memory from each input/output channel based on preset priorities, and the execution of the access requests is based on the priority of the corresponding channel. This is performed in the page mode when the number of data stored in the temporary storage memory reaches a preset number.

Therefore, data transfer from the circuit block to the dynamic random access memory can be performed without going through the microprocessor, and no interrupt processing overhead occurs. In addition, parallel operation of microprocessors and circuit blocks is possible, and access requests are executed in page mode, improving processing speed.

Further, in the invention corresponding to claim (2), the number of data stored in the temporary storage memory when executing the page mode can be arbitrarily set by the microprocessor.

Furthermore, in the invention corresponding to claim (3), when the number of data stored in the corresponding temporary storage memory is plural when an access request is executed, the access is performed in the page mode, and when the number of data is one, the access is performed in the single mode. Do it in mode.

Furthermore, in the invention corresponding to claim <4>, when the address to which a plurality of data stored in the temporary storage memory is to be written is within the same page on the dynamic random access memory, access is made in page mode. I will do it.

[Example code] Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

As shown in FIG. 1, a microprocessor 11, a ROM
(read-only memory) 12, receiving circuit 13 that receives print data (codes of characters to be printed, codes for printer control, etc.) sent from the host; communication circuit 14 that performs data communication with other devices; , an image data output circuit 1 that outputs image data to the printing section of a laser printer.
5. A dynamic RAM control circuit 17 for controlling a dynamic RAM (random access memory) 16 is provided. Note that the receiving circuit 13
, the communication circuit 14, and the image data output circuit 15 each constitute a circuit block.

In order to operate the dynamic RAM 16 normally, the dynamic RAM control circuit 17 uses a RAS (rath signal) for divided address input and refreshing.
, CAS (gas signal), WE (write enable signal), and other signal timings.

The dynamic RAM control circuit 17 has, for example, four input/output channels CH, CH2, CH3, CH4.
A system data bus 18 to which the microprocessor 11 and ROM 12 are connected is connected to the input/output channel CH, via a temporary storage memory 19 having a 4-word configuration, and the input/output channel CH2 is connected to the system data bus 18 to which the microprocessor 11 and ROM 12 are connected. A data bus 20 to which the receiving circuit 13 is connected is connected via a temporary storage memory 21 having a 27-code configuration, and a data bus 22 to which the communication circuit 14 is connected is connected to the input/output channel CH. The input/output channel CH4 is connected via a word-structured temporary storage memory 23, and a data bus 24 to which the image data output circuit 15 is connected is directly connected.

The dynamic RAM control circuit 17 controls each channel CH1 to CH4 based on a preset priority order.
The access requests from the server are executed sequentially.

Further, when two words of data are stored in the temporary storage memory 21 connected to the reception circuit 13 via the data bus 20, the dynamic RAM control circuit 17 transfers the data in the temporary storage memory 21 to the dynamic RAM.
16 is set to be accessed in page mode, for example, high speed page mode.

In addition to high-speed page mode, there are other page modes such as static column mode and nibble mode.
This mode is a mode in which multiple words are read and/or written in one cycle of access.

As shown in FIG. 2, the microprocessor 11 controls each circuit block including the dynamic RAM control circuit 17, that is, the microprocessor 11, the receiving circuit 13, the communication circuit 14, and the image data output circuit 15. Process A is started after setting and controlling the priority order and further setting and controlling the number of data required when accessing the data in the temporary storage memory 21 in page mode. Note that the channel CH used by the microprocessor 11 is set to have the highest priority.

In this embodiment with such a configuration, for example, a micro-
Describing the case where the processing A by the processor 11 and the reception processing of print data
During a fixed period of time, the microprocessor 11 uses the dynamic RAM 16 for processing A.

When the reception of the data X is completed, the reception circuit 13 writes the data X into the temporary storage memory 21 via the data bus 20. When the writing of data X is completed, reception of the next data Y is started.

At this time, since the processing A by the microprocessor 11 has a high priority, data X is not written to the dynamic RAM 16.

When the reception of the data Y is completed, the receiving circuit 13 stores the data Y in the temporary storage memory 21 via the data bus 20.
Write.

In this way, two words of data are stored in the temporary storage memory 21.

When processing A, which was being executed preferentially in this state, ends, the dynamic RAM control circuit 17 determines that 2 words of data are stored in the temporary storage memory 2 connected to channel CH2. Writing is performed to the dynamic RAM 16 in high-speed page mode.

The processing by the microprocessor 11, the processing by the receiving circuit 3, and the usage status of the dynamic RAM 16 at this time are shown in FIG.

FIG. 4 is a timing diagram showing the write control of the dynamic RAM control circuit 17 in the dynamic RAM 16 in the high-speed page mode. That is, it is sufficient to perform precharging once after writing data X and data Y.

Data X received by the receiving circuit 13 in this way.

Y can be transferred to the dynamic RAM control circuit 17 without using the microprocessor 11. Therefore, no interrupt processing is required, and no waiting time occurs.

Furthermore, while the receiving circuit 13 is receiving data and writing it into the temporary storage memory 21, the microprocessor 11 can execute processing A in parallel. Then, two words of data are stored in the temporary storage memory 21, and immediately after processing A by the microprocessor 11 is completed, the data in the temporary storage memory 21 is written to the dynamic RAM 6 by the dynamic RAM control circuit 17 in high-speed page mode. .

Therefore, it is possible to improve processing speed and processing efficiency.

Note that this embodiment is extremely effective in data multiplexing where the receiving circuit 13 always receives a plurality of pieces of data.

In the above embodiment, when processing A by the microprocessor 11 having a high priority in the dynamic RAM control circuit 17 is completed, the temporary storage memory 2 is
If 2 words of data are stored in 1, the data is written to the dynamic RAM 16 in high-speed page mode, but this is not necessarily the case. If there is a relatively large number of single-shot data processes, such as in the case of 1, the following data processing may be performed.

That is, when processing A by the microprocessor 11, which has a high priority as a dynamic RAM control circuit, is completed, the number of data stored in the temporary storage memory 21 is determined, and if there is a plurality of data, each data is written. When the address is within the same page on the dynamic RAM 16, the data is written to the dynamic RAM 16 in high-speed page mode, and when the number of data is one, the data is written in the dynamic RAM 16 in the dynamic RAM 16.
Write to AM16 in single page mode.

In this way, even if only one piece of data is stored in the temporary storage memory 21 when the process A by the microprocessor 11 is finished, the dynamic RAM
Since access to 16 can be executed immediately, it is extremely effective when multiple data processing and single-shot processing are mixed, and there are relatively many single-shot processings.

Further, in the above embodiment, the temporary storage memory 21 corresponding to the receiving circuit 13 has a 2-word configuration, and the temporary storage memory 23 corresponding to the communication circuit 14 has a 1-word configuration, and the number of data required when accessing in high-speed page mode. The following settings were made for the channel CH2 to which the temporary storage memory 21 is connected. For example, the temporary storage memory 23 corresponding to the communication circuit 14 also has a multi-word configuration, and the number of data required when accessing in high-speed page mode. Whether the setting is performed for the channel CH2 connected to the temporary storage memory 21 or for the channel CH connected to the temporary storage memory 23 can be changed by a command from the microprocessor 11. Good too.

[Effects of the Invention] As detailed above, according to the present invention, it is possible to provide a memory control device that can improve processing speed and processing efficiency.

[Brief explanation of drawings]

Figures 1 to 4 show an embodiment of the present invention; Figure 1 is a block diagram, Figure 2 is a flowchart showing main processing by a microprocessor, and Figure 3 is a process by a microprocessor. , processing by the receiving circuit and dynamic R
Figure 4 is a diagram showing the procedure of AM processing, Figure 4 is a diagram showing data write timing to dynamic RAM in high-speed page mode, Figures 5 to 7 are conventional examples, and Figure 5 is a block diagram. FIG. 6 is a diagram showing the timing of writing data to the dynamic RAM in single mode, and FIG. 7 is a diagram showing the procedure of processing by the microprocessor, processing by the receiving circuit, and processing of the dynamic RAM. 11... Microprocessor, 1 3... Receiving circuit (circuit block) 6... Dynamic RAM. 7...Dynamic RAM control circuit, 19°1. 3...Memory for temporary storage.

Claims (4)

[Claims] (1) Dynamic random access memory,
A dynamic controller has a plurality of input/output channels and controls access to the memory by controlling the timing of signals such as a ras signal, a gas signal, and a write enable signal to the memory.
A random access memory control circuit, and a plurality of temporary storage memories each having a plurality of words and provided for all or some of the input/output channels of the dynamic random access memory control circuit. , 1 of each temporary storage memory
The dynamic random controller consists of a microprocessor that controls one via a system data bus to write and read data, and the other circuit block that writes and/or reads data to and from temporary storage memory. - The access/memory control circuit sequentially executes access requests from each input/output channel based on preset priorities, and also temporarily stores access requests from input/output channels provided with a temporary storage memory. A memory control device that operates in page mode when the number of data stored in a memory reaches a preset number of data. (2) When the dynamic random access memory control circuit executes an access request for an input/output channel provided with temporary storage memory in page mode, the number of data required in the temporary storage memory can be freely set by the microprocessor. The memory control device according to claim 1, characterized in that: (3) Dynamic random access memory;
A dynamic controller has a plurality of input/output channels and controls access to the memory by controlling the timing of signals such as a ras signal, a gas signal, and a write enable signal to the memory.
A random access memory control circuit, and a plurality of temporary storage memories each having a plurality of words and provided for all or some of the input/output channels of the dynamic random access memory control circuit. , 1 of each temporary storage memory
The dynamic random controller consists of a microprocessor that controls one via a system data bus to write and read data, and the other circuit block that writes and/or reads data to and from temporary storage memory. - The access/memory control circuit sequentially executes access requests from each input/output channel based on preset priorities, and also temporarily stores access requests from input/output channels provided with a temporary storage memory. A memory control device characterized in that it operates in page mode when a plurality of pieces of data are available in a memory for temporary storage, and operates in a single mode when there is only one piece of data in its temporary storage memory. (4) A dynamic random access memory control circuit stores a plurality of data in a temporary storage memory, and the address to which each data is written is within the same page on the dynamic random access memory. 4. The memory control device according to claim 3, wherein the access request is executed in page mode.