JPH07281941A - Memory control method and device therefor - Google Patents

Abstract

PURPOSE:To attain the control of a memory with high performance by setting optionally the wait time when a fast access cycle can be carried out in response to the contents of the processing that is carried out with an access given to a control subject memory. CONSTITUTION:A DRAM control part 1 is connected to a system bus 4 and controls a memory 2 based on the address signal, the data signal and the control signal received from the bus 4. A wait control part 3 is connected to the bus 4 and the part 1. When Wait-END is asserted by the part 3 and also no access request is produced from the bus 4 or when the accesses are given to the different pages, Wait-clear is asserted to inform the part 3 of the cancel of a Wait state and also the shift to a RAS-OFF state. Then the RAS precharging is carried out. Thus the time us variable in the Wait state and therefore an operation optimum to a system can be ensured.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dynamic random access memory (hereinafter referred to as DRA) having a high speed access mode such as a high speed page mode and a static column mode.
(Referred to as “M”) and the like for a memory control device for controlling a memory.

[0002]

2. Description of the Related Art Today, DRAM is a semiconductor memory device that is widely used in computer systems and the like. In such a DRAM, when a DRAM capable of high-speed page mode operation is used, if the row address accessed is the same as the row address accessed immediately before, it is different from the normal read / write cycle. It is possible to execute a faster read / write cycle (high-speed access cycle) and improve the performance.

Further, when executing such a high speed access cycle, the wait time, which is the time during which the high speed access cycle from the current memory access to the next memory access can be executed, is fixedly determined.

[0004]

However, in general,
In a computer system, the optimum wait time differs depending on the processing executed. Therefore, as in the conventional case, in which the wait time is fixedly determined in advance, it is possible to perform control for a certain process so that the operation state becomes good, but execute another process. In this case, there is a problem that the performance is lowered.

However, in actual processing, it is often composed of various different processing groups. Therefore, high-performance memory control can be performed by the actual processing including such various processing groups. A memory controller was desired.

[0006]

In order to solve the above-mentioned problems, a memory control method and a memory control device of the present invention are provided.
In a memory control method and a memory control device that execute a high-speed access cycle, a wait time, which is the time during which a high-speed access cycle from the current memory access to the next memory access can be executed, is accessed to the memory to be controlled. It is characterized in that it is arbitrarily set according to the content of processing to be executed.

[0007]

In the memory control method and the memory control device of the present invention, when performing an arbitrary process, the optimum wait time is set according to the content of the process. For example, when a certain process is composed of a plurality of process groups, the optimum wait time is set for each process of the process group. When each process is performed, the wait time most suitable for the process is set and then executed, and when the next process is performed, the wait time corresponding to the process is set.

[0008]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is an explanatory diagram of a memory control method of the present invention. According to the memory control method of the present invention, the address of the memory is designated by the row address and the column address to perform the access, and when the next access to the memory is the same row address as this time, the access is performed only by the column address. A memory control method that executes a fast access cycle
The feature is that the wait time, which is the time during which a high-speed access cycle from the current memory access to the next memory access can be executed, is arbitrarily set according to the processing contents to be executed by accessing the memory. It is a thing. Then, FIG. 1 is a state transition diagram of the memory control device for explaining such a memory control method. Prior to the explanation of FIG. 1, the memory control device will be explained.

<< Structure of Memory Controller of Embodiment >> FIG. 2 is a block diagram showing the structure of the memory controller of the present invention. The illustrated apparatus includes a DRAM controller 1, a memory 2, and a weight controller 3. The DRAM control unit 1 is connected to the system bus 4 and controls the memory 2 based on an address signal, a data signal and a control signal from the system bus 4. In the figure, SAXX is an address bus in the system bus 4. Address signal, SDXX is a data signal of the data bus in the system bus 4, and Req and Ack are request signals and acknowledge signals in the control bus.

Further, the DRAM control unit 1 designates the address of the memory 2 with a row address and a column address for access, and if the next access to the memory 2 is the same row address as this time, the column control is performed. It executes a high-speed access cycle in which access is performed only by the address.

The memory 2 is a DRAM (dynamic RA).
M) and is configured to be controlled by the DRAM controller 1. The weight control unit 3 is a feature of the memory control device of the present invention, and is connected to the system bus 4 and the DRAM control unit 1 and is connected to the RA of the memory 2.
It is configured to manage the waiting time (number of in-page waits) while keeping S (row address strobe) active, and the details thereof are as follows.

FIG. 3 is a block diagram showing the internal structure of the weight control unit 3. The weight control unit 3 includes a weight register unit 31 including an n-bit register that can be set by software, a weight counter unit 32 including an n-bit counter, and a comparing unit 33 including an n-bit comparator.

The wait register unit 31 decodes a request from the system bus 4 by the DRAM control unit 1 and waits for it.
In response to the t register setting request WReq signal, SDXX data (Wait register setting value = W_
(Set) and write Set_E after writing.
The nd signal is used to notify the DRAM controller 1 of the end of writing.

Further, the weight counter section 32 is
When the Wait_Start signal from the M control unit 1 is received, it is configured to start incrementing the internal counter value in synchronization with the basic clock. Further, the comparison unit 33 uses the Wait register setting value (W_Set) and the Wait counter value (W_Count) as inputs of the internal comparators, respectively, and asserts Wait_End when the comparison results are equal, and the DRAM control unit 1
Is configured to notify.

Then, the weight counter unit 32 is
When the it_End is asserted or the Wait_Clear from the DRAM control unit 1 is asserted, the counter value is cleared and the next Wait_Start is waited.

FIG. 4 is a flow chart of the control operation of the weight controller 3. First, when the power is turned on, W_C
set count = 0 and initialize W_Set (step S1). When W_Set is initialized, it is assumed that it is set to a preset initial value. Then W_Se
It is determined whether t = W_Count (step S
2), if W_Set = W_Count is not satisfied, Wa
Deassert it_End (step S3). Then, it is determined whether or not it is Wait_start (step S4), and when it is not Wait_start, the process returns to step S2 to repeat the above processing.

Further, in step S2, W_Set
= W_Count, Wait_End is asserted (step S5), and the process returns to step S2.
It should be noted that such a process is performed when W_Set is 0, for example.

On the other hand, in the above step S4, Wai
If it is t_start, the weight counter unit 3
2 starts incrementing the internal counter value in synchronization with the basic clock (step S6). After that, W
It is determined whether _Set = W_Count (step S7). If W_Set = W_Count is not satisfied, W
It is determined whether it is ait_Clear (step S
8), if not Wait_Clear, step S
Returning to 6, continue incrementing the counter value.

When W_Set = W_Count, Wait_End is asserted (step S9), and W_Count is set to 0 (step S).
10) and returns to step S2. If it is Wait_Clear in step S8, the process proceeds to step S10 to set W_Count to 0.

Further, the state transition of the memory control device configured as described above is shown in FIG. 1. Before explaining the state transition, as a comparative example of the memory control device of the present invention, a high speed access is performed. A case in which the standby time during which the mode can be executed is fixed, that is, the case where the weight control unit 3 does not perform control will be described.

<< Structure of Comparative Example >> FIG. 5 is a block diagram showing the structure in that case. The configuration shown in the figure includes a DRAM control unit 101 and a memory 102.
1 is connected to the system bus 103. And D
The RAM control unit 101 has the same configuration as that shown in FIG. 2 except that the standby time is fixed in terms of hardware.

<< Operation of Comparative Example >> Next, the operation will be described. 6 and 7 are time charts thereof, and FIG. 8 is a state transition diagram. Normally, when the access from the system bus 103 does not occur, the DRAM control unit 1
01 waits in the idle (idle) state. Access from the system bus 103 is activated by a Req (request) signal, and when this is accepted, a Row-
It transits to the Adr state and responds with an Ack signal. still,
In the time charts of FIGS. 6 and 7, both Req and Ack are described as active low signals.

In the Row-Adr state, the DRAM control unit 101 outputs the Row address as the address signal MAXX to the memory 102 according to the address signal SAXX of the address bus on the system bus 103. Next RA
In the S-ON state, RAS is asserted and the Row address is latched in the memory 102. In FIG. 8, “a” between states indicates always (always). Next, transition to the Column-Adr state, and
Output the column address as MAXX.

CAS is asserted in the next CAS-ON state, and this Column address is latched in the memory 102. At this time, if it is a write, the data signal MDXX on the data bus is written in the memory 102. In the case of reading, the data signal MDXX is read from the memory 102 onto the data bus. This data is input / output by the data signal SDXX on the system bus.

Then, CAS is deasserted in the CAS-OFF state, and the access for one cycle is completed. At this time, if Req of the next cycle is asserted,
Whether or not the same page as in the immediately preceding cycle is accessed is determined by address comparison or a means similar thereto. Then, access to the same page (this is called Req.
If it is described as “Hit”, C is used without precharging RAS.
Return to the olu-Adr state, CAS-ON, C
AS-OFF is repeated and the cycle is executed in the fast page mode. In FIG. 8, “·” is a logical product, “/”
Indicates negation, and “+” indicates logical sum.

On the other hand, if Req is not asserted (described as / Req in FIG. 8), or if Req is asserted, access to a page different from the previous cycle (FIG. 8)
In the case of Req./Hit), the next Wait
Transition to -1 state. Here, the same judgment as the CAS-OFF state is executed, and the state transits to the Column-Adr state or the Wait-2 state. And
The same judgment is repeated and the state transits to the Wait-N state. In this state, if Req is not asserted, or if Req is asserted but the same page is not accessed, the RAS-OFF state is entered and RAS is deasserted. Idl from this state
Precharge RAS during the e-state (in Fig. 8, RA
S-PCH1, RAS-PCH2) is executed, and if the next cycle has come, the idle state is changed to Row.
-Adr ... transition is repeated.

The RAS-PCHs 1 and 2 are states for guaranteeing the RAS precharge time peculiar to the memory, and here, an example of the memory which requires the precharge time of 2 clocks is shown.

Further, in the above comparative example, when Req is asserted and an access is made to a page whose cycle is different, the transition to Wait-N is always made and then RAS-OFF.
It is transiting to the state, but from CAS-OFF to Wait
When this is detected in the t- (N-1) state, there is also one that jumps over the subsequent states and transits to the RAS-OFF state. The number N of Wait-1 to Wait-N is a fixed value of 0 or more and varies depending on the system.

In such a comparative example, the time (= wait time) for keeping RAS active and waiting, that is,
The number of weights remaining in a page (hereinafter referred to as the number of weights in a page, or simply the number of weights) is fixed in terms of hardware. Therefore, in a process in which the number of waits between successive accesses during actual program execution is larger than the number of waits set in advance by hardware, even if accesses to the same page continue, the RAS It goes to precharge and operates to stand by in the idle state. Therefore, in the worst case, RA
The access cycle becomes longer by the S precharge time and the input time of the Row address.

For example, when the cycle activated by the third Req shown in FIG. 7 is the access to the same page, this corresponds to this. In this case, comparing with the number of clocks from Req assertion to CAS assertion, it can be seen that an extra 5 clocks are spent compared to the second Req shown in FIG.

On the contrary, the number of set weights is made sufficiently large so that most accesses during actual program execution are
If you do not exceed this set weight number, this time,
If an out-of-page access occurs while waiting, RAS precharge is executed once, and after returning to idle,
Since the cycle is started, the start of the cycle is delayed by the RAS precharge time as compared with the case of waiting in the idle state. Therefore, in this case, the performance decreases as the number of out-of-page accesses increases.

This corresponds to the case where the third access in FIG. 7 is asserted at a timing one clock earlier, that is, the timing of 3A, and the cycle activated by this is access to a different page. In this case id
When waiting in the le state, that is, the first Re
It consumes 4 extra clocks compared to the response to q. As described above, when the number of weights is fixed, it is unavoidable that the above-mentioned state occurs.

On the other hand, the operation of this embodiment will be described with reference to FIG. << Operation of Embodiment >> First, the state transits in synchronization with the basic clock. Also in the present embodiment, when the access from the system bus 4 has not occurred, the DRAM control unit 1 uses idl
Wait in e-state.

Access from the system bus 4 is performed by Req
Signal, the address signal SAXX is decoded at this time, and if it is a Wait register setting request, WRe
Assert q and transit to the Wait_Set state. In the Wait_Set state, the weight control unit 3
At W, W_Set is written in the wait register unit 31, and after writing, Set_End is asserted. In response to this, the DRAM control unit 1 asserts Ack to the system bus 4 and returns to the idle state.

When the decoding result is memory access, MReq is internally asserted, the state transits to the Row-Adr state, and Ack is asserted. In addition, in FIG.
“A” indicates always (always). Then, the subsequent transition and control to the CAS-OFF state are the same as those in the above-described comparative example without the weight control unit 3, and C
After deasserting AS, one cycle of access ends.

When a memory access to the same page occurs (described as MReq.Hit in FIG. 1), C
Transition to the olu-Adr state and execute the fast page mode cycle. Further, when an access to a different page occurs (described as Req./Hit in FIG. 1, this includes access to the wait register 31), the RAS-OFF state is entered and the RAS precharge is performed. Run (RAS-PCH1,2), idl
Return to the e-state and perform the requested access.

If no access request is issued from the system bus (that is, / Req), Wait_
Except when End is asserted (that is, except when the setting value W_Set to the wait register unit 31 is 0), the state transits to the Wait state. At this time, W at the same time
Asserts ait_Start and notifies the wait control unit 3 that the Wait state is entered.

On the other hand, when Wait_End is asserted (that is, when W_Set is 0), RAS-
Transition to the OFF state and execute RAS precharge without waiting. At this time, Wait_Start is not asserted. In the Wait state, when a memory access (MReq · Hit) to the same page occurs, W
Assert ait_Clear to notify the weight control unit 3 that the wait state is exited, and
Transition to the lumn-Adr state and execute a fast page cycle.

In addition, the wait controller 3 causes Wait_
If End is asserted and the access request from the system bus 4 is not generated, or access to a different page is generated (/Req.Wait_
End + Req. / Hit) and Wait_Clear
Is asserted to notify the wait control unit 3 of the exit from the Wait state, the RAS-OFF state is entered, and the RAS precharge is executed. In other states (that is, / Req // Wait_End),
Stay in this state.

As described above, in this embodiment, since the time in the Wait state is variable, the optimum operation for the system can be performed. For example, when access to the same page occurs at a somewhat long time interval, the set value W_Set of the wait register 31 is set to a large value so that the cycle activated by the third Req in FIG. If so, the problem can be solved. On the other hand, when out-of-page access frequently occurs, W_Set can be reduced to prevent performance deterioration due to useless weight.

Since the operation of the above embodiment focuses on the RAS control method in the high speed mode of the DRAM, the description of the strict read / write control of the DRAM and the method of realizing the refresh cycle will be omitted. .

Next, in the memory control method of the above-described embodiment, for an arbitrary process, when a wait time corresponding to each actual process group included in the process is preset and the arbitrary process is executed, A case where the wait time is set at the start of each actual process will be described.

<< Example of Setting Number of Weights >> FIG. 9 shows an example of a program executed by the memory control device of the present embodiment, as an example of the arbitrary processing. This program (referred to as program S) is composed of processes A, B, C and D, and each process is made into a subroutine. FIG. 10 shows the contents of each process.

Each process is characterized by the access interval to the memory 2. For example, it is assumed that the actual process A shown in (a) is a process that frequently accesses different pages. In this case, it is more efficient to execute the RAS precharge immediately when there is no access and wait for the next cycle in the idle state, rather than waiting in the page. Therefore, the process A sets the weight register setting value W_Set to 0 (step S1),
After performing the actual process A (step S2), the value of the weight register 31 is returned to the initial value (step S3).

Further, the actual process B shown in (b) is a process in which memory accesses to the same page occur frequently, but other processes are inserted between the memory accesses and the access interval becomes long. To do. In this case, it is more efficient to wait within the page for as long as possible. Therefore, the process B is the weight register setting value W_S.
After setting et to 15 (step S1) and performing the actual process B (step S2), the value of the weight register 31 is returned to the initial value (step S3). The value 15 of the weight register setting value W_Set is the maximum value when the weight register 31 is composed of 4 bits.

Further, depending on the processing content, access to the same page may occur with a fixed number of waits or less, and if more waits are entered, access to different pages may occur frequently. . This is the case of the actual process C shown in (c), and therefore the process C
Sets the weight register setting value W_Set to 3 (step S1), performs actual processing C (step S2), and then returns the value of the weight register 31 to the initial value (step S).
3) Treat as processing. Here, it is assumed that the number of waits between accesses to the same page is 3 or less.

On the other hand, the access method may be completely random and cannot grasp the characteristics. This is designated as Process D. In this embodiment, the characteristics of the memory access are grasped by the processing contents in this way, and when the processing is executed, the number of in-page waits optimized for the processing is always set, and then the actual processing is executed. . The method of grasping the characteristics of memory access is by analyzing the processing contents of software.

Further, in this embodiment, the number of weights is returned to the initial value before returning to the main routine from each processing. As a result, if the memory access pattern is unknown as in the process D, the process is executed with the initial value without setting it in the subroutine. This initial value is not limited to a value initialized by hardware, and should be a value optimized for the system.

However, depending on the system and the processing contents, the processing itself for returning to the initial value may become an overhead, resulting in performance degradation. In such a case, it is possible to omit the process of returning to the initial value, and in that case, the process D is executed with the number of weights set in the process executed immediately before. Further, if it is desired to avoid being affected by the contents of the previous processing, it is possible to set the number of weights to an initial value before starting the actual processing of the processing D and then execute the actual processing.

Furthermore, the weight register 31, which limits the upper limit of the number of weights, the weight counter 32, and the bit number n of the comparison unit 33 are also values to be optimized by the system.
These optimum values are determined mainly by evaluation of performance. In some systems, the larger the number of weights, the better. In such a case, the weight can be managed by the refresh timer. In this case, for example, when the number of waits is set to the maximum value, it is possible to perform control such that waiting is continued within a page until RAS precharge is executed by a refresh request.

As described above, according to the above embodiment, RA
Since the setting of the number of waits in a page that waits while S is active is made variable, the characteristics of processing contents in terms of memory access are grasped, and the number of waits is set to an optimum value based on this processing contents for high-speed access. It is possible to obtain excellent access performance in a memory system using a DRAM that supports a mode.

For example, by applying it to the control of the frame memory in the graphic system, it is possible to set the optimum number of weights according to the drawing function. When applied to a system having a drawing function in hardware, the number of weights can be switched by hardware according to the drawing content. That is,
By providing a command analysis section instead of the weight register section 31 and providing a circuit for generating a W_Set value according to a drawing function (command), it is possible to perform hardware switching.

[0053]

As described above, according to the memory control method and the memory control device of the present invention, the wait time, which is the time during which the high-speed access cycle from the current memory access to the next memory access can be executed, Since the setting is made arbitrarily according to the processing contents to be executed by accessing the memory, it is possible to perform high-performance memory control corresponding to each processing even when performing various processing.

[Brief description of drawings]

FIG. 1 is an explanatory diagram of a memory control method of the present invention.

FIG. 2 is a block diagram showing a configuration of a memory control device of the present invention.

FIG. 3 is an internal configuration diagram of a weight control unit in the memory control device of the present invention.

FIG. 4 is a flowchart showing an operation of a weight control unit in the memory control device of the present invention.

FIG. 5 is a block diagram showing a configuration of a comparative example.

FIG. 6 is a time chart (No. 1) of a comparative example.

FIG. 7 is a time chart of a comparative example (No. 2).

FIG. 8 is a state transition diagram of a comparative example.

FIG. 9 is an example of a program executed by the memory control device of the present invention.

FIG. 10 is a diagram showing the content of each process of a program executed by the memory control device of the present invention.

[Explanation of symbols]

 1 DRAM control unit 2 Memory 3 Weight control unit 31 Weight register unit 32 Weight counter unit 33 Comparison unit

Claims (3)

[Claims] 1. A high-speed access for specifying a memory address by a row address and a column address, and accessing only the column address when the next access to the memory is the same row address as this time. In the memory control method for executing the access cycle, the wait time, which is the time during which the high-speed access cycle from the current memory access to the next memory access can be executed, is arbitrarily set according to the processing content to be executed by accessing the memory. A memory control method characterized by being set. 2. The memory control method according to claim 1, wherein a wait time corresponding to an actual processing group included in the process is preset for an arbitrary process, and the arbitrary process is executed. A memory control method, wherein the wait time is set when each of the actual processes is started. 3. A high-speed method for accessing a memory by designating a row address and a column address as a memory address, and when the next access to the memory is the same row address as this time, the memory is accessed only by the column address. In the memory control device that executes the access cycle, the wait register section that sets the wait time, which is the time at which the high-speed access cycle can be executed from this memory access, and the wait from this memory access when there is an arbitrary memory access. When there is an arbitrary memory access with the wait counter unit that starts counting time, the set time of the wait register unit is compared with the count value of the wait counter unit, and if they match, the high-speed access cycle A memo having a comparison unit for releasing Re-control device.