JPH04188345A - Memory controller - Google Patents

Abstract

PURPOSE:To improve processing speed and processing efficiency by executing the access request of an input/output channel provided with a temporary memory by a page mode by a dynamic RAM control circuit when the number of data stored in that memory reaches the preset number of the data. CONSTITUTION:The access request from a microprocessor 11 or a circuit block to the dynamic random access memory(RAM) control circuit 17 is executed by using the different input/output channels CH1 to CH4 respectively, and the data from the microprocessor 11 or the circuit block is stored in the temporary memories 19, 21, 23 of the corresponding channels CH1-3. Then, the control circuit 17 executes the access request from each input/output channel CH1-3 to a dynamic RAM 16, and this execution of the request is executed by the page mode when the number of the data stored in the corresponding temporary memories 19, 21, 23 reaches the preset number. Thus, the processing speed and the processing efficiency are improved, and in addition, sure data processing can be realized.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory control device applied to equipment using dynamic random access memory.

[Prior Art] For example, a memory control device shown in FIG. 7 is used in a laser printer. This memory control device includes a microprocessor 1, a ROM (read-only memory) 2, a receiving circuit 3 that receives print data (codes of characters to be printed, codes for printer control, etc.) sent from the host, and others. a communication circuit 4 that performs data communication with the device;
an image data output circuit 5 that outputs image data to the printing section;
Dynamic RAM (Random Access Memory)
The dynamic RAM control circuit 7 controls the RAM 6.

In order to operate the dynamic RAM 6 normally, the dynamic RAM control circuit 7 inputs divided addresses and inputs RAS (ras signal) and CAS for refreshing.
It is designed to control the timing of signals such as (cass signal) and WE (write enable signal).

The microprocessor 1, ROM 2, receiving circuit 3, communication circuit 4, image data output circuit 5, dynamic RAM
The control circuits 7 are connected to each other by a system data bus 8.

The print data received by the receiving circuit 3 is always written into the dynamic RAM 6 once, or the writing is controlled as follows.

When the receiving circuit 3 finishes reading the print data, it issues an interrupt request to the microprocessor 1.

When the microprocessor 1 receives an interrupt request, it saves the state of the routine being executed up to that point (i.e., the data stored in registers, the status of the task being executed, etc.) on the dynamic RAM 6, and stores it in the dynamic RAM 6. Transfers control to the role-inclusive processing routine. (Interrupt preprocessing) In the interrupt processing routine, the microprocessor 1
First, the data received from the receiving circuit 3 is read, and then the address at which the data should be stored is calculated and written into the dynamic RAM 6.

When the interrupt processing routine ends, the microprocessor 1 returns the state of the previously executed routine from the dynamic RAM 6 and transfers control to that routine.

In this way, conventionally, the receiving circuit 3 is configured using the dynamic RAM 6.
All data transfer between the receiving circuit 3 and the dynamic RAM 6 was performed by the microprocessor 1, without performing an equivalent active operation.

Furthermore, in the past, since the dynamic RAM control circuit 7 had only one input/output channel, only the circuit block that had the right to use the system data bus 8, that is, the microprocessor 1, could access the dynamic RAM 6.

The conventional dynamic RAM control circuit 7 reads or writes one word, or both, in one cycle of access in single mode (ie, leave cycle, early write cycle, delayed write cycle, read modify write cycle, etc.). mode) can be executed, so writing to consecutive addresses also involves repeating the single mode.

Therefore, when data X and data Y are written into the dynamic RAM 6, the timing is shown in FIG. In other words, there is a precharge time for each data write.

FIG. 9 shows the processing of the microprocessor 1, the processing of the receiving circuit 3, and the usage status of the dynamic RAM 6 when processing A by the microprocessor 1 and receiving processing of print data X and Y by the receiving circuit 3 proceed simultaneously. There is.

For example, processing A by the microprocessor 1 and the receiving circuit 3
Assuming that the reception of data X by
Microprocessor 1 uses dynamic RAM 6 for processing A during a certain period of time required to receive data X.

When the reception of data X is completed, an interrupt request is generated from the receiving circuit 3 to the microprocessor 1. Upon receiving an interrupt request, the microprocessor 1 writes the data X received by the receiving circuit 3 into the dynamic RAM 6 by sequentially performing interrupt pre-processing, reading and writing processing, and post-interrupt processing.

The receiving circuit 3 receives data X received by the microprocessor 1.
At the same time as the reading of data Y ends, it becomes operational and starts receiving the next data Y.

Furthermore, when the reception of data Y is completed, an interrupt request is generated from the receiving circuit 3 to the microprocessor 1. However, at this point, the microprocessor 1 is still in the middle of post-interrupt processing and cannot immediately start the next interrupt processing routine.

After that, when the engraving request is accepted, the microprocessor 1 writes the data Y received by the receiving circuit 3 into the dynamic RAM 6 by sequentially performing interrupt preprocessing, readout, write processing, and postinterrupt processing. .

When all interrupt processing related to received data X and Y is completed, the rest of the interrupted processing A is executed.

[Problems to be Solved by the Invention] As described above, in conventional memory control devices, the overhead of interrupt processing is large, and since dynamic RAM is accessed only in single mode, the processing speed is slow, and the time required to start accessing is slow. There were problems with long waiting times and low processing efficiency.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a memory control device that can improve processing speed and processing efficiency, and can also perform reliable data processing.

[Means for Solving the Problems] The present invention has a dynamic random access memory and a plurality of input/output channels, and controls the timing of signals such as a last signal, a dregs signal, and a write enable signal to the memory. A dynamic random access memory control circuit that controls access to memory, and one or more words provided for all or some of the input/output channels of this dynamic random access memory control circuit. A word-structured temporary storage memory, a microprocessor that controls one of the temporary storage memories via a system data bus to write and read data, and a microprocessor that writes data to and from the remaining temporary storage memories. Alternatively, a circuit block that performs reading or both, a temporary storage data detection circuit that detects the existence of data in each temporary storage memory, and a temporary storage data detection circuit that detects the existence of write data in the temporary storage memory. The dynamic random access memory control circuit executes access requests from each input/output channel and also handles temporary storage. An access request for an input/output channel provided with a temporary storage memory is executed in page mode when the number of data stored in the temporary storage memory reaches a preset number of data.

[Operation] In the present invention having such a configuration, access requests to the dynamic random access memory control circuit from the microprocessor or circuit block are made using different input/output channels. Data from the microprocessor or circuit block is stored in the temporary storage memory of the corresponding channel.

The dynamic random access memory control circuit executes access requests to the dynamic random access memory from each input/output channel,
The access request is executed in page mode when the number of data stored in the temporary storage memory of the corresponding channel reaches a preset number.

Therefore, data transfer from the circuit block to the dynamic random access memory can be performed without going through the microprocessor, and no interrupt processing overhead occurs. In addition, parallel operation of microprocessors and circuit blocks is possible, and access requests are executed in page mode, so processing speed can be improved.

Furthermore, when the temporary storage data detection circuit detects that write data exists in each temporary storage memory, the microprocessor control circuit inhibits the microprocessor from reading data from the memory.

[Example] Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

Microprocessor] 1. ROM as shown in Figure 1
(Read-only memory) 12, Receiving circuit 13 that receives print data sent from the host (codes of characters to be printed, codes for printer control, etc.), Communication circuit 14 that performs data communication with other devices , an image data output circuit that outputs image data to the printing section of a laser printer]
5. A dynamic RAM control circuit 17 for controlling a dynamic RAM (random access memory) 16 is provided. Note that the receiving circuit 13
, the communication circuit 14, and the image data output circuit-15 each constitute a circuit block.

In order to operate the dynamic RAM 16 normally, the dynamic RAM control circuit 17 uses a RAS (rath signal) for divided address input and refreshing.
, CAS (cass signal), WE (write enable signal), and other signal timings.

The dynamic RAM control circuit 17 has, for example, four input/output channels CH, CH2, CH3, CH.
, is connected to the input/output channel CH, via a system data bus 18 to which the microprocessor 11 and ROM 12 are connected, or one temporary storage memory having a 3-word configuration, and to the input/output channel CH2. A data bus 20 connected to the receiving circuit 13 is connected via a temporary storage memory 21 having a two-word structure, and a data bus 22 connected to the communication circuit 4 is connected to the input/output channel CH. The data bus 24 to which the image data output circuit 15 is connected is directly connected to the input/output channel CH.

The dynamic RAM control circuit 17 controls each channel CH, to CH4 based on a preset priority order.
The access requests from the server are executed sequentially.

Furthermore, when two words of data are stored in the temporary storage memory 2 connected to the reception circuit 13 via the data bus 20, the dynamic RAM control circuit 17 transfers the data in the temporary storage memory 21 to the dynamic RAM.
1.6 is set to be accessed in page mode, for example, high speed page mode.

In addition to high-speed page mode, there are other page modes such as static column mode and nibble mode F.
This mode is a mode in which multiple words are read and/or written in one cycle of access.

As shown in FIG. 2, the microprocessor 11 controls each circuit block including the dynamic RAM control circuit 7, that is, the microprocessor 11, the receiving circuit 13, the communication circuit 14, and the image data output circuit 15. Process A is started after setting and controlling the priority order and further setting and controlling the number of data required when accessing the data in the temporary storage memory 21 in page mode. Note that the channel CH used by the microprocessor 11 is set to have the highest priority.

Further, a temporary storage data detection circuit 2 detects the existence of data in each of the temporary storage memories 19, 21, and 23.
5 is provided, and when this temporary storage data detection circuit 25 detects that write data exists in the temporary storage memory 19, 21, 23, it supplies a detection signal S1 to the microprocessor control circuit 26. .

When the microprocessor control circuit 26 receives the detection signal S1 from the temporary storage data detection circuit 25, the microprocessor control circuit 26 controls the microprocessor 11 to control the microprocessor 11.
A read inhibit signal S2 for inhibiting data read from the dynamic RAM 16 by the dynamic RAM 16 is supplied.

Note that the microprocessor 11 has a dynamic R
When data is written to AM1.6, the data is supplied to the dynamic RAM control circuit 17 via the temporary storage memory 19, and the dynamic RAM control circuit 17 is
When reading data from the AM 16, the data is directly read out from the dynamic RAM control circuit 17, bypassing the temporary storage memory 19.

In this embodiment with such a configuration, for example, when the processing A by the microprocessor 11 and the reception processing of print data During a certain period of time, the microprocessor 11 uses the dynamic RAM 16 for processing A.

When the reception of the data X is completed, the reception circuit 13 writes the data X into the temporary storage memory 21 via the data bus 20. When the writing of data X is completed, reception of the next data Y is started.

At this time, since the processing A by the microprocessor 11 has a high priority, the data X for the dynamic RAM 16 is
is not written.

When the reception of the data Y is completed, the receiving circuit 13 stores the data Y in the temporary storage memory 21 via the data bus 20.
Write.

In this way, two words of data are stored in the temporary storage memory 21.

When processing A, which was being executed preferentially in this state, is completed, the dynamic RAM control circuit 17 determines that 2 words of data are stored in the temporary storage memory 21 connected to channel CH2, and performs high-speed processing. Writing is performed to the dynamic RAM 16 in page mode.

The processing by the microprocessor 11, the processing by the receiving circuit 3, and the usage status of the dynamic RAM 16 at this time are shown in FIG.

FIG. 4 is a timing diagram showing the write control of the dynamic RAM control circuit 17 in the dynamic RAM 16 in the high-speed page mode. That is, it is sufficient to perform precharging once after writing data X and data Y.

Data X received by the receiving circuit 13 in this way.

Y can be transferred to the dynamic RAM control circuit 17 without using the microprocessor 11.

Therefore, no interrupt processing is required, and no waiting time occurs.

Furthermore, while the receiving circuit 13 is receiving data and writing it into the temporary storage memory 21, the microprocessor 11 can execute processing A in parallel. Then, two words of data are stored in the temporary storage memory 21, and immediately after the processing A by the microprocessor 11 is completed, the data in the temporary storage memory 21 is dynamically read by the dynamic RAM control circuit 17 in a high-speed page mode.
Written to AM16.

Therefore, processing speed and processing efficiency can be improved.

Note that this embodiment is extremely effective in data multiplexing where the receiving circuit 13 always receives a plurality of pieces of data.

Furthermore, for example, the microprocessor 11 may
Writing data to address OOO for AM16,
When the processing of writing data to address XXX and writing data to address △△△ is executed sequentially, each data is temporarily stored in the temporary storage memory 19 and then sequentially read out by the dynamic RAM control circuit 17. Writing is performed to the dynamic RAM 16.

Therefore, if data at address ΔΔΔ is read from the microprocessor 11 at the time when the dynamic RAM control circuit 17 has finished writing data to the dynamic RAM 16 at address OOQ, a temporary error occurs as shown in FIG. Reading of data at address △△△ will be started while the data to address XXX and the data to address Δ△△ still remain in the storage memory 19, and the data at address △Δ△ before being changed will be started. An inconvenience occurs in that data is read out.

Therefore, in this embodiment, as shown in FIG.
It is detected that data to address ΔΔΔ and data to address ΔΔΔ remain. As a result, the microprocessor control circuit 26 prohibits the microprocessor 1 from reading data.

Therefore, the microprocessor 11 will not read data from the dynamic RAM 16 while only the data for the address XXX and the data for the address ΔΔΔ remain in the temporary storage memory ]9.

After that, when the dynamic RAM control circuit 17 finishes writing data to address XXX and address △△△ in the dynamic RAM 16, the data disappears from the temporary storage memory 19, so the microprocessor control circuit 26 The command cancels the prohibition on the microprocessor 11 from reading data.

In this way, the microprocessor 11 uses dynamic RAM.
Only data at address △△△ can be read from 16. The data at address △△△ at this time is data that has been changed by writing and is correct data. In this way, reliable data processing can be performed.

In the embodiment described above, the microprocessor 1 having a high priority in the dynamic RAM control circuit 17
] When processing A is completed, the temporary storage memory 21
If two words of data are stored in the memory, the data is written to the dynamic RAM 16 in high-speed page mode, but this is not necessarily the case. If the data is to be processed once or in a relatively large amount, the following data processing may be performed.

In other words, when processing A by the microprocessor 11 having a high priority as a dynamic RAM control circuit is completed, the number of data stored in the temporary storage memory 21 is determined, and if the number of data is plural, the address to which each data is written is determined. or within the same page on the dynamic RAM 16, the data is stored in the dynamic RAM 16.
Writes to AM16 in high-speed page mode, and when the number of data is 1, the data is written to dynamic RA
M], 6 in single page mode.

In this way, even if only one piece of data is stored in the temporary storage memory 2 when the process A by the microprocessor 11 is completed, the dynamic RAM 1
6 can be immediately executed, which is extremely effective when multiple data processing and single-shot processing coexist and there are relatively many single-shot processings.

Further, in the above embodiment, the temporary storage memory 21 corresponding to the receiving circuit [3] has a 2-word configuration, and the temporary storage memory 23 corresponding to the communication circuit] 4 has a 1-word configuration, which is necessary when accessing in high-speed page mode. The number of data has been set for the channel CH2 to which the temporary storage memory 21 is connected, but for example, the temporary storage memory 23 corresponding to the communication circuit 14 is also configured with multiple words, which is necessary when accessing in high-speed page mode. It is possible to change by a command from the microprocessor 11 whether the setting of the number of data is to be performed for the temporary storage memory 21 and the connected channel CH2, or for the temporary storage memory 23 and the connected channel CH3. You can.

[Effects of the Invention] As described in detail above, according to the present invention, it is possible to provide a memory control device that can improve processing speed and processing efficiency, and can also perform reliable data processing.

[Brief explanation of the drawing]

1 to 6 show an embodiment of the present invention. FIG. 1 is a block diagram, FIG. 2 is a flowchart showing the main processing by the microprocessor, and FIG. 3 is the processing and reception by the microprocessor. Processing by circuit and dynamic RAM
FIG. 4 is a diagram showing the timing of writing data to dynamic RAM in advanced page mode. FIG. 5 is a diagram for explaining the operation when reading is not prohibited. FIG. Figures 7 to 9 are diagrams for explaining the operation when inhibition is performed, and show conventional examples. Figure 7 is a block diagram, and Figure 8 shows the data write timing for dynamic RAM in single mode. The diagram shown in FIG. 9 shows processing by a microprocessor, processing by a receiving circuit, and dynamic RAM.
It is a figure which shows the procedure of a process. 11... Microprocessor, 13... Receiving circuit (circuit block), 16... Dynamic RAM. 17...Dynamic RAM control circuit, 19
．． 21.23...Memory for temporary storage, 25...Temporary storage data detection circuit, 26...Microprocessor control circuit. Applicant's agent Patent attorney Takehiko Suzue

Claims (1)

[Claims] A dynamic random access memory having a plurality of input/output channels, and controlling access to the memory by controlling signal timings of a ras signal, a cass signal, a write enable signal, etc. to the memory. A dynamic random access memory control circuit, and a one-word or multiple-word temporary memory provided for all or some of the input/output channels of the dynamic random access memory control circuit. memory for temporary storage, and one memory for each temporary memory.
a microprocessor that controls one via a system data bus to write and read data, a circuit block that writes and/or reads data to and from the remaining temporary memory memories, and each of the temporary memory memories. a temporary storage data detection circuit for detecting the existence of data in the temporary storage memory; and a temporary storage data detection circuit for detecting the existence of write data in the temporary storage memory; The dynamic random access memory control circuit includes a microprocessor control circuit that prohibits reading, and the dynamic random access memory control circuit executes access requests from each input/output channel, and also processes access requests from input/output channels provided with temporary storage memory. A memory control device characterized in that execution is performed in page mode when the number of data stored in the temporary storage memory reaches a preset number of data.