JPH05334176A - Memory access system - Google Patents

Abstract

PURPOSE:To shorten the delay of the access time of a CPU and a bus master to a memory. CONSTITUTION:At the time of detecting the transfer of bus using right from the CPU to the bus master or the bus master to the CPU based upon a change in a sub arbitration signal, a bus request signal from the bus master, a bus release permission signal from the CPU, or the like, a DMA detecting circuit 21 outputs a bus right transfer signal (a) to an OR gate 22 and informs a DRAM controller 23 of the transfer of the bus using right. Then the controller 23 turns a RAS signal to an inactive state for a certain time prior to the address determination of the succeeding access and then ends a page mode. If the bus using right is not transferred, the controller 23 holds the RAS signal in an active state until the succeeding access to continue the page mode.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory access system in a computer system in which a CPU, a bus master and the like obtain a right to use a bus for access.

[0002]

2. Description of the Related Art FIG. 8 shows a CPU 11 and a DRAM 12.
, Bus master 13, and LSI 1 such as ROM and RAM
It is a block diagram of the computer system which consists of 4 etc.

In this system, the right to use the bus is the CPU
DR that is passed from 11 to the bus master 13 or from the bus master 13 to the CPU 11 and obtains the bus use right
The AM 12 can be accessed.

When programs and data are stored in the DRAM 12, the CPU 11 mainly accesses the program area, and the bus master 13 often accesses the data area. Generally, a program and data are stored in separate areas, and their storage addresses are stored in the DRAM 12
It will be a different page above.

For example, when the memory access by the CPU 11 and the bus master 13 are alternately performed as shown in FIG. 9, a page change occurs every time the memory access by the CPU 11 and the memory access by the bus master 13 are performed.

Further, as shown in FIG. 10, the bus master 13
When a certain amount of data is burst-transferred, the number of page changes is small, but the page changes occur when the bus usage right shifts from the bus master 13 to the CPU 11 or from the CPU 11 to the bus master 13. Is.

FIG. 11 is a circuit diagram of a DRAM control device based on the conventional memory access method. The row address (RA; Ro
w Address) is retained. The comparator 16 compares the current row address with the previous row address held in the address latch 15, and determines whether the row address matches or does not match the DRA.
Notify the M controller 17.

The DRAM controller 17 includes the DRAM 1
2 is a circuit for performing access control, refresh control, etc. for the row address 2. When a row address match signal is output from the comparator 16, the RAS signal is kept active to continue the memory access in the page mode and When the non-coincidence signal is output, the RAS signal is made inactive for a certain period of time to cause the address latch 15 to latch a new row address.

In the page mode, the RAS signal is activated, the CAS signal is activated to complete one access, and then the CAS signal is temporarily deactivated to change the column address. The CAS signal is activated to access a memory cell in another column in the same row, and memory access can be performed faster than a normal read or write cycle.

The multiplexer 18 multiplexes the row address RA and the column address CA and outputs them to the DRAM 12.

[0011]

The operation timing in the conventional memory access system when the CPU 11 and the bus master 13 are alternately accessed will be described with reference to FIG.

When the DRAM 12 is accessed by the bus master 13 after the access of the DRAM 12 by the CPU 11 and the row addresses of the two are different, that is, when the page is changed, a low-level address mismatch signal is output from the comparator 16 described above. It is output to the DRA controller 17.

The DRAM controller 17 includes a comparator 16
When the low level address mismatch signal from
The RAS signal is made inactive after being deactivated for a certain time (T1 time), but in this case, it is necessary to activate the RAS signal after a certain precharge time has elapsed.

Therefore, in the conventional memory access method,
A wait cycle of T1 hours is inserted in the access cycle of the bus master 13 to secure the precharge time of the RAS signal.

After the access of the bus master 13, the CPU 1
Even if 1 is accessed, if there is a page change, the T
It is necessary to insert a wait cycle for one hour.

That is, in the conventional memory access method, when DRAMs are accessed from both the CPU and the bus master and page changes occur frequently, a wait cycle of T1 hours is inserted in each access cycle. As a result, there is a problem that the access time becomes long and the program execution time and the data transfer time are delayed.

An object of the present invention is to reduce delay in access time due to memory access by a CPU or a bus master.

[0018]

FIG. 1A is an explanatory view of the principle of the first invention. In a system in which a CPU or a bus master obtains a right to use a bus to access a memory, the detection means 1 uses a bus arbitration signal such as an address confirmation signal, a bus master's bus request signal, or a CPU's bus release permission signal. It is detected that the usage right of the CPU is transferred from the CPU to the bus master or from the bus master to the CPU.

When the detecting means 1 detects that the bus use right has been transferred, the control means 2 deactivates the RAS signal before the address of the next access is fixed, and terminates the page mode.

FIG. 1B is an explanatory view of the principle of the second and third inventions. The portion surrounded by the one-dot chain line is a principle explanatory diagram corresponding to the second invention, and the whole is a principle explanatory diagram corresponding to the third invention.

In the second invention, the CPU address storage means 3 stores the latest row address accessed by the CPU, and the bus master address storage means 4 stores the latest row address accessed by the bus master.

When the detecting means 1 detects that the bus usage right has been transferred, the comparing means 5A stores the row address stored in the CPU address storing means 3 and the bus master address storing means 4. Compare the row address.

As a result of the comparison in the comparison means 5A, the control means 2A keeps the RAS signal active and continues the page mode if the row addresses match. Before the access address is determined, the RAS signal is made inactive for a predetermined time to end the page mode.

In the third invention, the address storage means 6
Stores the row address of the last access. When the detection means 1 detects that the bus usage right has been transferred, the comparison means 5B stores the row address stored in the CPU address storage means 3 or the bus master address storage means 4 and the address storage means 6. The line address immediately before is compared.

As a result of the comparison by the comparison means 5B, the control means 2B keeps the RAS signal active and continues the page mode when the row addresses match. Before the row address for the access is determined, the RAS signal is deactivated to end the page mode.

[0026]

In the first aspect of the present invention, when the right to use the bus is transferred from the CPU to the bus Matus or from the bus master to the CPU, the RAS signal is made inactive for a certain period of time before the next access cycle starts. CP
The memory access time can be greatly shortened when the page is frequently changed by the access between U and the bus master.

In the second and third inventions, when the bus use right is transferred to the CPU or the bus master, for example, the CPU
Alternatively, if the latest row address accessed by the bus master matches the row address of the previous access, the page mode access is continued, and if the row address does not match, the RAS signal is deactivated for a certain period of time before the next access cycle starts. I am trying to do it.

Therefore, if the same row address is likely to be accessed even if the right to use the bus is transferred, page mode access is enabled to shorten the memory access time, and the same row address is If the possibility of being accessed is low, the page mode can be ended before the next access cycle to shorten the memory access time.

[0029]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 2 is a circuit configuration diagram of a main part of the DRAM control device according to the first embodiment of the present invention.

In the figure, the same circuit blocks as those of the conventional circuit shown in FIG. 11 are designated by the same reference numerals, and their description will be omitted. The overall configuration of the computer system to which the DRAM control device of the embodiment is connected is similar to that shown in FIG.

The DMA detection circuit 21 includes a bus master and a C
PU address confirmation signal, bus master bus request signal,
It is a circuit that detects a change in a bus arbitration signal such as a bus release permission signal of the CPU and determines that the right to use the bus is transferred from the CPU to the bus master or from the bus master to the CPU. The DMA detection circuit 21 normally outputs a high-level bus right transfer signal a to the OR gate 22, and when it detects that the right to use the bus has been transferred, it outputs a low level bus right transfer signal a. Output to.

The comparator 16 receives the address latch 15 according to a control signal from a DRAM controller 23 which will be described later.
This is a circuit that compares the upper address (row address RA) of the previous (one cycle before) address latched in the row address with the row address in this access, and when the row addresses do not match, a low level address mismatch signal. b is output to the OR gate 22. When the comparator 16 does not compare the row address, the high level address mismatch signal b is output.

In the OR gate 22, the bus right transfer signal a output from the DMA detection circuit 21 and the comparator 16 are output.
The address mismatch signal b output from the above is input, and when either one of the signals becomes the low level, the page mode cancel signal c of the low level is output to the DRAM controller 23.

The DRAM controller 23 is a DRAM
(See FIG. 8) Output of a row address strobe signal (RAS signal), a column address strobe signal (CAS signal), a write enable signal (WE signal) that controls writing, and refresh control are performed. Circuit.

Next, the operation when the CPU or the bus master obtains the right to use the bus to access the DRAM will be described with reference to the operation time chart of FIG. It should be noted that the address confirmation signal, the RAS signal, the CAS signal, the bus request signal, the bus release permission signal, the page mode cancel signal c, and the like, which will be described below, are low-level active signals.

The DRAM controller 23 activates the RAS signal (low level) when the address confirmation signal of the CPU becomes active (low level) (FIG. 3, I).

If the CPU detects that the bus request signal of the bus master has become active (low level) and recognizes that there is an access request from the bus master, the CPU releases the bus when the access is completed. Passes the bus usage right to the bus master by activating the signal (low level).

In the DRAM detection circuit 21, the address determination signals of the CPU and the bus master are inactive (high level), the bus request signal of the bus master is active (low level), and the bus release permission signal of the CPU is active (low level). If it is detected that the bus right has been transferred from the CPU to the bus master, the low-bell bus right transfer detection signal a is sent to the OR gate 22.
Output to.

At this time, since the address mismatch signal b from the comparator 16 input to the other input terminal of the OR gate 22 is at high level, the low level bus right transition detection signal a is at low level in the page mode. DR output to the DRAM controller 23 as a cancel signal c
When the AM controller 23 detects that the page mode cancel signal c has become low level, the AM controller 23 makes the RAS signal inactive (high level) for a predetermined time (T1 time) and ends the page mode (FIG. 3, II).

After deactivating the RAS signal for a certain period of time to secure the precharge time of the RAS signal,
When the address confirmation signal of the bus master becomes active, the RAS signal becomes active (FIG. 3, III).

That is, when the right to use the bus is transferred from the CPU to the bus master, the access from the CPU is completed until the access to the bus master is started.
Since the RAS signal is inactive for a certain time (T1 time) to secure the precharge time of the RAS signal, a wait cycle is inserted in the access cycle of the bus master to make the RAS signal inactive for a certain time as in the conventional case. Access time can be shortened.

If the current access is the CPU and the next access is also the CPU, that is, if the right to use the bus is not transferred, the page mode is likely to be valid, so the RAS signal remains active. To

When the access of the bus master is completed and the bus request signal of the bus master is inactive and the bus release permission signal of the CPU is inactive, the bus use right is transferred from the bus master to the CPU.

If the DMA detection circuit 21 detects that the address confirmation signals of the CPU and the bus master are inactive, the bus request signal of the bus master is inactive, and the bus release permission signal of the CPU is inactive,
It is determined that the bus mastership is transferred from the bus master to the CPU, and the low-level bus mastership detection signal a is output to the OR gate 22.

This low level bus right transition detection signal a
Is output to the DRAM controller 23 as a page mode cancel signal c. DRAM controller 23
Detects that the page mode cancel signal c has become a low level, it deactivates the RAS signal for a certain period of time to end the page mode (IV in FIG. 3).

If the RAS signal is inactive for a certain period of time to secure the precharge time, the RAS signal is activated when the CPU address confirmation signal becomes active (V in FIG. 3).

As described above, in the first embodiment, when the right to use the bus is transferred from the CPU to the bus master or from the bus master to the CPU, before the next access is started, that is, before the next address is determined. In addition, since the RAS signal is inactive for a certain period of time to secure the precharge time of the RAS signal, there is no need to insert a wait cycle during the next access to make the RAS signal inactive as in the conventional case. The access time can be shortened accordingly.

By the way, the CPU and the bus master are connected to the DRA.
When M is alternated or randomly accessed, CPU
There is a case where the page of the DRAM accessed by and the page of the DRAM accessed by the bus master match.

FIG. 4 shows the CPU even if the right to use the bus is transferred.
If the page accessed by the bus master and the page accessed by the bus master are likely to match each other, the page mode is continued. Otherwise, R is executed before the next access cycle.
D of the second embodiment of the invention for deactivating the AS signal
FIG. 3 is a circuit configuration diagram of a main part of a RAM control device.

In the figure, the CPU address latch 31
Is the latest CPU access (last access last)
The upper address (row address) of the DRAM is stored in the bus master address latch 32. The bus master address latch 32 is a circuit for storing the latest row address (first last access) accessed by the bus master. The row address at that time is latched according to.

Further, the address latch 15 and the comparator 16 compare the row address of the previous access stored in the address latch 15 with the row address of the current access as described above, and the two match. This is a circuit for determining whether or not to do.

The comparator 33 compares the latest row address accessed by the CPU stored in the CPU address latch 31 and the previous row address stored in the address latch 15 in accordance with the control signal from the DMA detection circuit 35. This is a circuit for comparison and outputs a low level CPU address mismatch signal d to the DMA detection circuit 35 when the addresses do not match.

Similarly, the comparator 34 includes the DMA detection circuit 3
Bus master address latch 3 according to the control signal from 5
2 is a circuit for comparing the latest row address accessed by the bus master stored in 2 with the previous row address stored in the address latch 15. When the addresses do not match, a low level bus master address mismatch signal e is output. Output to the DMA detection circuit 35.

The DMA detection circuit 35 includes an address confirmation signal for the CPU and the bus master, a bus request signal for the bus master,
Based on the bus arbitration signal such as the bus release permission signal of the CPU, it is determined whether the next access is the CPU or the bus master, and the comparator 33 or 34 is instructed to compare the row address. Further, it detects the low level CPU address mismatch signal d or the bus address mismatch signal e output from the comparators 33 and 34 and outputs the low level address mismatch signal f to the OR gate 36.

The OR gate 36 has a DMA detection circuit 35.
The address non-match signal f from the comparator 16 and the address non-match signal a from the comparator 16 are input, and when either one of the signals is at the low level, the low level bage mode cancel signal g is sent to the DRAM controller 37. Output.

The DRAM controller 37 outputs a row address strobe signal (RAS signal), a column address strobe signal (CAS signal), a write enable signal (WE signal) for controlling writing, and the like for controlling the fetch timing of the DRAM address. This is a circuit for performing refresh control of the DRAM.

Next, the operation of the above DRAM controller will be described with reference to the operation time chart of FIG. When it is detected that the address confirmation signal of the CPU becomes active in the access cycle of the CPU, the DMA detection circuit 3
5, the CPU address latch 31 is instructed to latch the row address, and the row address accessed by the CPU at that time is stored in the CPU address latch 31. Further, after the comparison of the previous row address stored in the address latch 15 by the comparator 16 and the current row address is completed, the current CPU address is latched in the address latch 15 (FIG. 5, I). ..

When the CPU detects that the bus request signal of the bus master has become active and recognizes that the bus master has requested the bus, it activates the bus release permission signal when the access is completed, Pass the bus usage right to the bus master.

If the DMA detection circuit 35 detects that the address confirmation signals of the CPU and the bus master are inactive, the bus request signal of the bus master is active, and the bus release permission signal of the CPU is active, the bus is used. It judges that the right has been transferred from the CPU to the bus master, and instructs the comparator 34 to compare the row addresses.
In response to this, the comparator 34 receives the latest row address accessed by the bus master stored in the bus master address latch 32 and the row address of the last access stored in the address latch 15 (in this case, one cycle before). The row address accessed by the CPU) is compared.

Here, the comparator 34 compares the latest row address accessed by the bus master with the row address one cycle before. The reason is that if the next access is a bus master, the bus master will access the last one. Since the same row address as the specified row address is likely to be accessed, the latest row address of the bus master is compared with the immediately preceding row address, and if they match, the next access will also cause DRAM in page mode. This is for continuing the access of.

When the latest row address accessed by the bus master and the row address at the time of the previous access (one cycle before) match, the bus master address mismatch signal e output from the comparator 34 remains high level. Therefore, the DMA detection circuit 35 outputs a high level address mismatch signal f.

As a result, if the row addresses match, the page mode cancel signal g input to the DRAM controller 37 remains at the high level, and the DRAM
The RAS signal output from the controller 37 remains active until the access cycle of the next bus master, and the DRAM is accessed in the page mode.

On the other hand, when the latest row address accessed by the bus master and the row address at the time of previous access do not match, the comparator 34 outputs the low level bus master address mismatch signal e. DMA detection circuit 35
When it detects that the bus master address mismatch signal goes low, it outputs a low level address mismatch signal to the OR gate 26.

As a result, when the row addresses do not match, the page mode cancel signal g input to the DRAM controller 37 becomes low level, and the RAS signal output from the DRAM controller 37 becomes inactive for a certain period of time. This secures the precharge time of the RAS signal (FIGS. 5, II and III).

If the next access is the CPU,
That is, if the bus use right does not shift, the page mode is likely to be valid, so the DRAM controller 37 keeps the RAS signal active and continues the page mode.

The bus master deactivates the bus acquisition signal when the access is completed, and the bus mastership becomes C.
Pass to PU. If the DMA detection circuit 35 detects that the address confirmation signals of the CPU and the bus master are inactive, the bus request signal of the bus master and the bus release permission signal of the CPU are inactive, and the bus acquisition signal of the bus master is inactive. , It is judged that the bus use right is transferred from the bus master to the CPU, and the comparator 33 receives the CP.
An instruction is given to compare the latest row address accessed by the CPU, which is stored in the U address latch 31, with the row address at the time of the previous access, which is stored in the address latch 15.

In the case of CPU access as well, like the bus master, it is highly likely that the same row address as the last row address accessed by the CPU will be accessed in the next access, so it is stored in the CPU address latch 31. Comparing the latest (first and last) row address accessed by the existing CPU with the previously accessed row address stored in the address latch 15 (in this case, the row address accessed by the bus master one cycle before). And the next C
Before the address is determined by the PU access, it is determined whether or not the page mode is continued.

When the latest row address accessed by the CPU and the row address at the time of the previous access (one cycle before) match, the high-level CPU address is output from the comparator 33 as in the accelerator of the bus master described above. Since the non-coincidence signal d is still output, the RAS signal output from the DRAM controller 37 remains active until the next CPU access cycle, and the DRAM is accessed in the page mode.

On the other hand, if the latest row address accessed by the CPU and the row address at the time of the previous access do not match, the comparator 33 outputs the low-level CPU address mismatch signal d, so the DRAM controller 3
The RAS signal output from 7 becomes inactive, and the page mode access ends (FIG. 5, IV). In the following, also in the subsequent access cycle, the latest row address of the CPU or the bus master is compared with the row address of the previous access at the time when the bus usage right is transferred, and whether the page mode is continued or terminated. Is judged.

In the above embodiment, when it is detected that the bus right has been transferred, it is compared whether or not the latest row address accessed by the CPU or the bus master matches the row address at the time of access one cycle before. However, if they match, the same row address is likely to be accessed in the next CPU or bus master access.
The page mode is continued with the RAS signal kept active, and if the row addresses do not match, the RAS signal is deactivated and the page mode is ended before the address of the next access cycle is determined. ..

As a result, when the latest row address of the CPU or the bus master does not match the row address of one cycle before, the RAS signal is deactivated before the next access cycle. It is not necessary to insert a wait cycle during access to deactivate the RAS signal, and the DRAM access time can be shortened accordingly.

Further, when the latest row address of the CPU or the bus master matches the row address of one cycle before, for example, when the program arranged in the DRAM and the page of data accessed by the bus master match. , The RAS signal is kept active to continue the page mode, so that the access time of the DRAM can be further shortened.

Even if the latest row address of the bus master or the CPU matches the previous row address, the actual row address may not match the previous row address. That is, the next access is the bus master, the latest row address accessed by the bus master matches the previous row address, but the row address actually accessed by the bus master does not match the previous row address. In the CPU, the latest row address accessed by the CPU matches the previous row address, but the row address actually accessed by the CPU does not match the previous row address. In this embodiment, the CPU is used only in these cases.
Alternatively, the RAS signal is precharged during the access of the bus master.

Next, FIG. 6 shows the DRA of the third embodiment of the present invention.
It is a circuit block diagram of the principal part of an M control apparatus. This embodiment shows a circuit configuration when the number of address latches in the second embodiment of FIG. 4 is reduced by one. Hereinafter, the same circuit blocks as those in FIG. 4 will be assigned the same reference numerals and explanations thereof will be omitted.

In FIG. 6, the comparator 41 has a D
According to the instruction from the MA detection circuit 42, the latest row address accessed by the CPU stored in the CPU address latch 31 is compared with the latest row address accessed by the bus master stored in the bus master address latch 32, and both are compared. If they do not match, a high-level address mismatch signal h is output, and if they do not match, a low-level address mismatch signal h is output to the DMA detection circuit 42. Note that the comparator 41 normally outputs a high-level address mismatch signal.

The DMA detection circuit 42 is a circuit for detecting the shift of the bus use right from the change of the bus arbitration signal such as the address confirmation signal, the bus request signal of the bus master, and the bus release permission signal of the CPU. When it is detected that the right has been transferred, the comparator 41 is instructed to compare the row addresses. Further, the DMA detection circuit 42 includes a comparator 4
When the low level address mismatch signal h output from 1 is detected, the low level address mismatch signal f ₁ is output to the OR gate 45.

The comparators 43 and 44 are the DMA detection circuit 42.
The current row address and the bus master address latch 32 or C when the address is determined according to the control signal from
This is a circuit for comparing the immediately preceding row address latched by the PU address latch 31.

For example, if the last access was to the bus master, the comparator 43 compares the latest row address accessed by the bus master stored in the bus master address latch 32 with the current row address. If they match, the high level address mismatch signal b ₁ is output to the OR gate 45, and if they do not match, the low level address mismatch signal b ₁ is output to the OR gate 45.

If the last access was to the CPU, the comparator 44 compares the latest row address accessed by the CPU stored in the CPU address latch 31 with the current row address. If they match, a high-level address mismatch signal b ₂ is output to the OR gate 45, and if they do not match, a low-level address mismatch signal b ₂ is output to the OR gate 45.

The DRAM controller 46 is basically the same as the circuit of FIG. 4, and performs DRAM read / write timing control, refresh control, and the like. The DRAM controller 46 outputs R when the page mode cancel signal g ₁ output from the OR gate 45 is at high level.
The page mode is continued with the AS signal kept active, and when the page mode cancel signal g ₁ is low, the RAS signal is deactivated to end the page mode.

That is, in the above DRAM controller,
At the time when the transfer of the right to use the bus is detected (before the address of the next access is determined), the comparator 41 compares the latest row address accessed by the bus master with the latest row address accessed by the CPU. If the row addresses match, the RAS signal remains active and the page mode is continued. If the row addresses do not match, the RAS signal is set before the row address for the next access is determined.
The signal is made inactive to terminate the page mode. Further, when the row address is determined in the next access cycle, the row address determined by the comparator 43 or 44 at that time and the bus master address latch 32 or C.
The row address stored in the PU address latch 31 at the immediately preceding access is compared, and when the actual row address matches, the page mode access is performed as it is. When the actual row address does not match, the access is performed during the access. A wait cycle is inserted and the RAS signal is deactivated, ending the page mode access.

Next, the operation of the DRAM control device will be described with reference to FIG.
Will be described with reference to. After the CPU access is completed, C
Address determination signals of PU and bus master are inactive, bus request signal of bus master is active, and C
When it is detected that the PU bus release permission signal has become active, the DMA detection circuit 42 determines that the bus use right is C
When it is determined that the PU has shifted to the bus master, the comparator 41 is instructed to compare the row addresses.

As a result, the comparator 41 causes the latest (first-last) row address accessed by the bus master stored in the bus master address latch 32 and the latest row address accessed by the CPU stored in the CPU address latch 31. Compare with the row address of.

If the row addresses match as a result of this comparison, it is highly likely that the same row address will be accessed in the next access by the bus master. Therefore, the DRAM controller 46 keeps the RAS signal active, and It enables DRAM access in page mode even in the bus master access cycle. At this time, if the row addresses do not match, the RAS signal is made inactive for a predetermined time (T1 time) to end the page mode (FIGS. 7, II and III).

At this time, if the next access is a CPU access, the page mode is likely to be valid, so the comparator 41 does not perform comparison, and the RAS signal remains active until the next access cycle. Leave it and continue page mode.

Next, when the bus master access is completed,
If it is detected that the address confirmation signal of the CPU and the bus master is inactive, the bus request signal of the bus master is inactive, and the bus release permission signal of the CPU is inactive, the DMA detection circuit 42 determines that Judges that the bus master has transferred to the CPU, and instructs the comparator 41 to compare the row address.

In this case as well, as in the case of the bus master access described above, the comparator 41 determines the CPU address latch 31.
The latest row address accessed by the CPU is compared with the latest row address accessed by the bus master of the bus master address latch 32. If the row addresses match as a result of this comparison, the same row address is likely to be accessed in the next access by the CPU.
M controller 46 RAS until the next access cycle
Activates the signal to enable DRAM access in page mode. At this time, if the row addresses do not match, the RAS signal is made inactive for a certain period of time to end the page mode (FIG. 7, IV, V).

It should be noted that when the respective addresses are determined by the next access of the bus master or the CPU, the comparator 43
Alternatively, the comparator 44 compares the row address in the immediately previous access (one cycle before) with the confirmed row address, and when the row addresses do not match, the RAS signal becomes inactive during the access.

That is, in the comparison of the row address before the address is determined, the latest row address accessed by the bus master and the latest row address accessed by the CPU match, but the row address actually accessed by the bus master is Only when the row address of the immediately preceding access does not match or when the row address actually accessed by the CPU does not match the row address of the immediately preceding access, a wait cycle is inserted during the access of the CPU or the bus master, and RA
The S signal becomes inactive.

In addition to the effect of the second embodiment described above, this embodiment can reduce the number of address latches,
High-speed memory access can be realized with a simpler circuit configuration than the second embodiment.

In the above embodiment, the address confirmation signal of the CPU and the bus master, the bus request signal of the bus master,
Although it is detected that the right to use the bus has been transferred due to a change in the CPU bus release permission signal, etc., the transfer of the right to use the bus is detected without using all of the above signals or from other signals. It may be done. Also, CPU
The present invention can be applied not only to one bus master but also to a plurality of bus masters.

[0092]

According to the present invention, the RAS signal is made inactive before detecting the transfer of the right to use the bus from the CPU to the bus master or from the bus master to the CPU, and before the address of the next access cycle is determined. Since the page mode is terminated in this manner, there is no need to insert a wait cycle in the next access cycle to deactivate the RAS signal, and the memory access time can be shortened. Further, the latest row address accessed by the CPU and the bus master is stored, and when the bus use right is transferred from the CPU to the bus master or from the bus master to the CPU, for example, those row address and the row of the immediately preceding access are stored. When the row address is compared with the address and the RAS signal remains active, the page mode access is continued, and when the row address does not match, before the address of the next access is determined. By canceling the page mode, the memory access time can be further shortened.

[Brief description of drawings]

FIG. 1A is a diagram illustrating the principle of the first invention, and FIG. 1B is a diagram illustrating the principle of the second and third inventions.

FIG. 2 is a circuit configuration diagram of the DRAM control device of the first embodiment.

FIG. 3 is an operation time chart of the first embodiment.

FIG. 4 is a circuit configuration diagram of a DRAM control device of a second embodiment.

FIG. 5 is an operation time chart of the second embodiment.

FIG. 6 is a circuit configuration diagram of a DRAM control device of a third embodiment.

FIG. 7 is an operation time chart of the third embodiment.

FIG. 8 is a configuration diagram of a computer system.

FIG. 9 is an operation explanatory diagram when the CPU and the bus master are alternately accessed.

FIG. 10 is an operation explanatory diagram when the bus master performs burst transfer.

FIG. 11 is a circuit configuration diagram of a conventional DRAM control device.

FIG. 12 is an operation time chart of a conventional memory access method.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 detection means 2, 2A, 2B control means 3 CPU address storage means 4 bus master address storage means 5A, 5B comparison means 6 address storage means

Claims (3)

[Claims] 1. In a system in which a CPU or a bus master obtains a bus use right to access a memory, the bus use right is transferred from the CPU to the bus master or from the bus master to the CP due to a change in the bus arbitration signal.
When the detection means (1) for detecting the shift to U and the shift of the right to use the bus are detected by the detection means (1), the RAS signal is set to a predetermined value before the address of the next access is determined. A memory access method, comprising: a control means (2) that is inactive for a certain period of time to end the page mode. 2. In a system in which a CPU or a bus master obtains a bus use right to access a memory, the bus use right is transferred from the CPU to the bus master or from the bus master to the CP due to a change in the bus arbitration signal.
Detecting means (1) for detecting the shift to U and CP for storing the latest row address accessed by the CPU
U address storage means (3), bus master address storage means (4) for storing the latest row address accessed by the bus master, and when the detection means (1) detects that the bus usage right has been transferred, A comparing means (5A) for comparing the row address stored in the CPU address storing means (3) with the row address stored in the bus master address storing means (4), and the comparing means (5A). If the row addresses match as a result of the comparison, the RAS signal remains active and the page mode is continued. If the row addresses do not match, the RAS signal is output for a predetermined time before the address for the next access is determined. And a control means (2A) for deactivating the page mode and ending the page mode. 3. In a system in which a CPU or a bus master obtains a right to use a bus to access a memory, the right to use the bus is C
PU to bus master or bus master to CPU
Detecting means (1) for detecting the shift to (1) and the CP for storing the latest row address accessed by the CPU
U address storage means (3), bus master address storage means (4) for storing the latest row address accessed by the bus master, address storage means (6) for storing the row address in the immediately preceding access, and the detection means When it is detected in (1) that the right to use the bus has been transferred, the row address stored in the CPU address storage means (3) or the bus master address storage means (4) and the address storage means (6). Comparing means (5B) for comparing with the immediately preceding row address stored in
As a result of the comparison by the comparing means (5B), if the row addresses match, the RAS signal remains active to continue the page mode. If the row addresses do not match, the next access is performed. RAS before the row address is fixed
A memory access method comprising: a control unit (2B) that deactivates a signal to end the page mode.