JPH0797814B2 - Memory controller - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a communication device having a memory bank composed of a plurality of memories, and more particularly to a memory control device suitable for use in a color facsimile or the like.

2. Description of the Related Art FIG. 6 shows an example of a conventional memory control device of this type.

FIG. 6 shows a schematic structure of a conventional memory device applied to a color facsimile. This device is a memory including a plurality of dynamic memories (DRAM), for example, R memory 1, G memory 2 and B memory 3. A bank, a refresh control unit 4 for the bank, a read / write control unit 5 for controlling the read / write of the R, G, B memories 1, 2, 3 and the R, G, B
The read / write control section 5 and the selector 9 are provided with a microprocessor (CPU) (CPU bus 10), which comprises a selector 9 for switching the input / output data buses 6, 7, 8 of the memories 1, 2, 3 The memory selection control signal 11 is input to switch the R, G, B memories 1, 2 and 3 by software processing of the CPU (program execution of the CPU).

Problems to be Solved by the Invention As described above, in the conventional memory control device, since the switching process of each memory of the memory bank is executed by the program of the CPU, the memory of several μs is inevitable when the memory is switched. Switching processing time is required. FIG. 7 illustrates this.

Therefore, in this type of conventional memory control device, when the memory output data is DMA-transferred to the high-speed communication control unit (not shown) via the selector input / output data bus 12 (see FIG. 6), each memory There is a problem that the transfer processing time becomes long due to a break in the output data.

Further, in order to solve the problem, it is necessary to prepare a buffer memory for absorbing the fluctuation of the transfer processing time in the communication control unit which is the transfer destination of the data from the memory (selector input / output data bus 12). is there. Therefore, there arises a problem that the circuit scale increases.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a memory control device that can switch each memory of a memory bank at high speed by hardware processing without increasing the circuit scale. To do.

Means for Solving the Problems In order to solve the above problems, the present invention provides a memory bank in which a plurality of memories in which unique patterns are periodically written are arranged in the same address space, and a plurality of the memory banks. Selector for switching the input / output data bus of each memory, a pattern detection unit for detecting a unique pattern written in each memory, and a reference table composed of a set of reference blocks including a transfer address and a transfer word number of the memory. A direct memory access controller (DMAC), a means for switching the memory by changing the selection state of the input / output data bus of the selector by a pattern detection signal from the pattern detection unit, and the memory switching In sync with the above
A means for updating the reference block of the reference table of the DMAC is provided, and each memory is switched by the pattern detection signal by hardware processing.

Action The present invention does not require software processing time for switching each memory as in the conventional case, because a plurality of memories are switched by hardware processing with the above configuration. Therefore, the buffer memory for absorbing the fluctuation of the processing time of software is not required. Therefore, speeding up of data transfer can be realized without increasing the circuit scale.

Embodiment FIG. 1 is a schematic block diagram showing an embodiment of a memory control device according to the present invention. In this embodiment, an application example to a color facsimile is shown.

In FIG. 1, 21 is an R memory (DRAM), 22 is a G memory (DRAM), and 23 is a B memory (DRAM). These R, G, B memories 21, 22, 23 are arranged in the same address space. In general, a plurality of memory banks are provided.
In the following description, when simply referred to as a memory, it means that the R, G, B memories 21, 22 and 23 are included.

24 is an input / output data bus of the B memory 23 (hereinafter referred to as B data bus), 25 is an input / output data bus of the G memory 22 (hereinafter referred to as G data bus), and 26 is the R memory 21.
I / O data bus (hereinafter referred to as R data bus), 27
Is a selector for selectively switching these data buses 24, 25, 26 (16 bits each) based on the data in the memory and the data (described later) written in the memory, and 28 is the input / output data of the selector 27 It's a bus.

29 is a memory switching pattern written in the memory (hereinafter,
It is called a unique pattern. Details will be described later. ) Is a pattern detection unit, 30 is an output signal of the detection unit 29,
It becomes an input signal to the selector 27 and the read / write controller 31 of the memory.

32 is a read / write control signal (RWE) of the R memory 21, 33
Is a read / write control signal (GWE) of the G memory 22, 34 is a read / write control signal (BWE) of the B memory 23, 35 is a write enable signal (WE), and WE35 is a control bus 36.
Is output from.

37 is a memory refresh control unit, 38 is an address bus for inputting a memory address to the memory, 39 and 40 are control signals (RAS, CAS) for accessing the memory, 41 is an address bus, and 42 is a ROM and RAM. Storage unit, 43 is a microprocessor (CPU), 44 is direct memory access
The controller (DMAC) 45 is a data bus.

FIG. 2 shows allocation (structure) of internal data to each of the R memory 21, G memory 22 and B memory 23 arranged on the same memory address a1 space.

Inside each R, G, B memory 21, 22, 23, a pattern for memory switching, so-called unique pattern 21a, 21b, 22a, 22b, 23a,
23b is written periodically in the memory data, that is, every predetermined address.

In this embodiment, each line (first line, second line,
..) internal data (R) of each R, G, B memory 21, 22, 23 for each
Component first line image data, R component second line image data,
The unique patterns 21a, 21b, ... Are written in the last portion of the G component first line image data ,.

FIG. 3 is a time chart showing the switching timing of the memory. In FIG. 3, 46 is a pattern detection signal in the pattern detection unit 29 for instructing the detection of the unique pattern written in the memory. Is the output signal of the pattern detection unit 29
Corresponds to 30. 47 to 49 are memory input / output data buses
A control signal for instructing which data bus of 24 to 26 is selected, 47 is a select signal instructing to select the R memory 21, 48 is a select signal instructing to select the G memory 22, and 49 is a select signal. This is a select signal for instructing to select the B memory 23.

The shaded portion in the select signal 47 is the input / output data bus of the R memory 21 in the section by the pattern detection signal 46.
Shows that 24 is selected. Similarly, the shaded portion in the select signal 48 is the input / output data bus 25 of the G memory 22, and the shaded portion in the select signal 49 is B.
The input / output data buses 26 of the memory 23 are shown to be selected.

In short, when data is read from the memory, the selection state of the input / output data buses 24 to 26 of the memory is changed by the pattern detection signal 46 from the pattern detection unit 29 in each of the shaded areas. That is, memory switching is performed by pattern detection by hardware processing.

50 is data from the memory (first line data A1, A2, A
3, the transfer of the second line data B1, ...) and at that time
The reference table referenced by the DMAC44 (hereinafter referred to as the link array
The table 51 shows the correspondence with 51 (see FIG. 4).

The link array table 51 is provided in the DMAC 44, and is referred to when the DMAC 44 or the CPU 43 accesses the memory to transfer data. As shown in FIG. 4, the first line data A1, References corresponding to the number of data of each line, such as reference blocks A1, A2, A3 corresponding to A2, A3 and reference blocks B1, B2, B3 corresponding to data B1, B2, B3 of the second line. Blocks are grouped for each line, and they are connected in series.

As shown in FIG. 4, the internal structure of each of the reference blocks A1, A2, ... Is a memory address (memory transfer address).
And a transfer word number (transfer word number) and a link address.

The memory address is an address at which the DMAC 44 starts data transfer, the transfer word number indicates how many words are transferred from the memory address, and at a predetermined address, that is, a cycle of the unique pattern written in the memory. Set to correspond. The link address is, for example, a pointer indicating which reference block of the table should be referred to after the transfer of the reference block A1 is completed.

Here, the same memory address a1 is written in the memory addresses of the reference blocks A1 to A3. That is, the memory address (for example, a1) written in the reference block, for example, A (A = A1, A2, A3) is the same for n consecutive reference blocks (for example, A1, A2, A3). , Reference blocks having the same memory address are continuously referred to by the number of memories.

FIG. 5 shows the position of the memory control device according to the present invention in the color facsimile in this embodiment. In the figure, 60 is a color scanner, 61 is a color printer, 62 is a memory control device according to the invention (see FIG. 1), 63
Is a communication control unit, 64 to 66 are R, G, B data signals written in the memory from the color scanner 60, 67 to 69 are R, G, B data signals from the memory to the color printer 61, and 70 is a memory control unit 6
Input / output data signal to 2 and input / output data signal 71 to the line. On the line, the signal 71 is transmitted for each R, G, B1 line.

Next, the memory control device configured as described above (see FIG. 1 to FIG.
The operation will be described below (see FIG. 4).

First, when reading data from the R memory 21, G memory 22, and B memory 23, the memory address is transferred from the DMAC 44 to the address bus.
It is output to 41, and the write enable 35 becomes "H" level. At this time, the output of the read / write controller 31 RWE32, GWE33,
All of BWE34 are also at "H" level. That is, all the memories are in the read state, and the data of the memory address is read from the address bus 38 onto the R data bus 26, the G data bus 25, and the B data bus 24.

Output signal 30 of pattern detection unit 29 (pattern detection signal 46)
Selects the R memory 21 as the initial setting. Therefore, the data of the R data bus 26 is output to the input / output data bus 28 of the selector 27.

The DMAC 44 continues the transfer operation while updating the memory address to be read until the transfer of the number of transfer words written in the link array table 51 of FIG. 4 is completed.

On the other hand, the selection state of the memory does not change until the unique pattern written in the memory (see FIG. 2) is read out.
With the memory 21 selected, the data is output onto the data bus 28. When the peculiar pattern is read out, the pattern detection signal 46 of FIG. 3 is generated inside the detection unit 29, and the selector 2 is selected as shown by the select signals 47 and 48 of FIG.
7 output changes from R memory 21 to G memory 23. That is, the selection state of the memory input / output data buses 24 to 26 is changed by the pattern detection signal 46 from the pattern detection section 29 (in this case, the G data bus 25 is selected). At the same time, the DMAC 44 is linked. The reference of the reference block A1 of the array table 51 is ended, the next reference block A2 is referred to, and the transfer is continued. That is, the DMAC 44 executes data transfer while updating the reference block of the link array table 51.

Since the updated reference block A2 and memory address are the same memory address a1 as the reference block A1, again,
Transfer starts from the same address space.

At this time, since the selector 27 is in the selected state of the G data bus 25, only the data on the G data bus 24 of the R data bus 26, the G data bus 25, and the B data bus 24 is input / output to / from the selector 27. It is output on the data bus 28.

When this operation is continued and the peculiar pattern written in the memory is detected, the selection state of the selector 27 is changed from the G memory 22 to the B memory 23 as shown by the selection signals 48 and 49 in FIG.

By repeating this, the data in the R, G, B memories 21 to 23 are output line by line on the input / output data bus 28 of the selector 27.

During this time, the CPU 43 does not perform the program processing for memory switching. That is, in the processing of the hardware, the memory switching is executed by detecting the unique pattern written in the memory. In synchronization with this, the link array table 51 of the DMAC 44 is also switched by software processing.

Next, the write operation to the memory will be described. When writing to memory, input data is input / output data bus 28 of selector 27
Input from. The input data on the data bus 28 is determined based on the output signal 30 (pattern detection signal 46) of the pattern detection unit 29, which memory data bus 24-26 is to be loaded.

Here, it is assumed that the output signal 30 of the pattern detection unit 29 selects the R data bus 26 as an initial setting. The memory selection signal 30 is also input to the read / write control unit 31, where the control signal RWE3 corresponding to the memory to be written is supplied.
Any of 2, GRE33, BRE34 goes to "L" level.

Since the R memory 21 is initially selected, the RWE 32 is at "L" level, and the others are at "H" level. Therefore, R memory 21
Is in the write state, and the other G, B memories 22 and 23 are in the read state.

In this case, writing to the memory is performed by referring to the link array table 51 in FIG. 4 as in the case of the above-mentioned reading.

When the pattern detection unit 29 detects the unique pattern, the unique pattern is written in the memory, and then the selection state of the selector 27 is changed from the R memory selection state to the G memory selection state.
The reference block of the link array table 51 also changes from A1 to A2.

That is, when the peculiar pattern is written in the memory, the selection state of the memory data buses 24-26 of the selector 27 is changed by the hardware processing and the memory switching is executed. At the same time
The reference block of the link array table 51 of the DMAC 44 is also switched and updated by software processing.

In this state, the data from the selector 27 is the G memory.
Written on 23. The switching of the link array table 51 by software processing and the switching operation of the memory data buses 24-26 by hardware processing are synchronized.

Writing to the memory is performed by repeatedly executing the above operation. The inside of the written memory has a data structure as shown in FIG.

As described above, even when writing to the memory,
Similar to the reading, the CPU 43 is not executing the program processing for memory switching.

EFFECTS OF THE INVENTION As is apparent from the above description, the present invention switches the input / output data bus of the memory bank based on the data in the memory and the unique pattern written in the memory. Moreover, there is no need for software processing for switching the memory, and the speed of data transfer processing can be increased without increasing the circuit scale.

[Brief description of drawings]

FIG. 1 is a schematic configuration block diagram showing an embodiment of a memory control device according to the present invention, FIG. 2 is a data allocation diagram showing an example of a data structure inside the memory, FIG. 3 is a memory switching timing diagram, FIG. FIG. 4 is a structural diagram of a link array table (reference table), FIG. 5 is a block diagram showing a schematic structure of a color facsimile to which the present invention is applied, and FIG. 6 is a block showing a schematic structure of a conventional memory controller. FIG. 7 and FIG. 7 are conceptual diagrams for explaining the processing time of memory switching. 21 …… R memory, 22 …… G memory, 23 …… B memory, 21
a, 21b, 22a, 22b, 23a, 23b …… Specific pattern (memory switching pattern), 24 …… B memory input / output data bus (B data bus), 25 …… G memory input / output data bus (G data) Bus), 26 ... R memory input / output data bus (R data bus), 27 ... selector, 29 ... pattern detection unit,
31 ... Read / write control block, 44 ... Direct memory access controller (DMAC), 51 ... Link array table (reference table), a1 ... Memory address (memory transfer address).

Claims (1)

[Claims] 1. A memory comprising a plurality of memories in which a unique pattern is periodically written and arranged in the same address space,
It comprises a selector for switching the input / output data buses of the plurality of memories, a pattern detection unit for detecting the unique pattern written in each memory, and a set of reference blocks including the transfer address and the transfer word number of the memory. Direct memory access controller (DMAC) equipped with a look-up table and memory switching by changing the selection state of the input / output data bus of the selector according to the pattern detection signal from the pattern detection unit. And a control unit for updating the reference block of the DMAC reference table in synchronization with the memory control device.