JPS62214769A - Memory control device - Google Patents

Abstract

PURPOSE:To attain high-speed switching of each memory of a memory bank by applying hardware processing to switch each memory by a pattern detection signal in a color facsimile equipment equipped with the memory bank comprising plural memories. CONSTITUTION:When a memory address is outputted to an address bus 41, data of the memory address is read from an address bus 38 onto R, G, B data buses 26, 25 24. An output signal 30 of a pattern detection section 29 selects a R memory 21 as the initial setting and data of the bus 26 is outputted to an input/output data bus 28 of a selector 27. In reading a specific pattern written on the memory, a pattern detection signal is generated in the inside of the detection section 29, the output of the selector 27 is changed to a G memory 23 and only the data on the bus 24 is outputted to the bus 28. The operation above is repeated and the specific pattern is detected, then the selective state of the selector 27 in the B memory 23 is changed. Through the repetition of above operations, the data in the memories 21-23 is outputted to the bus 28 at each line.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a communication device equipped with a memory bank consisting of a plurality of memories, and particularly to a memory control device suitable for use in color facsimiles and the like.

Conventional technology An example of a conventional memory control device of this type is shown in FIG.

FIG. 6 shows a schematic configuration of a conventional memory device applied to a color facsimile. A bank, its refresh control unit 4, and the R, G, B memories 1, 2 .
Read/write control unit 5 that controls read/write of No. 3
and a selector 9 for switching the input/output data bus 6°7.8 of the R9G and B memories 1, 2.3, and the read/write controller 5. ! : to selector 9,
The memory selection control signal 11 of the microprocessor (CPU) (CPU bus 10) is input, and the J
It is configured to switch between G and B memos IJ 1, 2, and 3.

Problems to be Solved by the Invention As described above, in the conventional memory control device, since the switching process of each memory of the memory bank is executed by the CPU program, it is inevitable that the memory switching process of several μs will occur when switching the memory. Switching processing time is required.

FIG. 7 illustrates this.

Therefore, in this type of conventional memory control device, when memory output data is DMA transferred to a high-speed communication control unit (not shown) via the selector input/output data bus 12 (see FIG. 6), each memory There is a problem in that the transfer processing time becomes longer due to breaks in the output data.

In addition, in order to solve this problem, it is necessary to prepare a buffer memory to absorb fluctuations in transfer processing time in the communication control unit that is the destination of data transfer from the memory (selector input/output data bus 12). be. Therefore, a problem arises in that the circuit scale increases.

The present invention has been made in view of the above-mentioned problems, and an object of the present invention is to provide a memory control device that can switch each memory of a memory bank at high speed by hardware processing without increasing the circuit scale. do.

Means for Solving the Problems In order to solve the above-mentioned problems, the present invention provides a memory bank in which a plurality of memories written in a periodic (-) memory are arranged in the same address space; A reference device comprising a selector for switching input/output data buses of a plurality of memories, a pattern detection section for detecting a unique pattern written in each of the memories, and a set of reference blocks including transfer addresses and the number of transfer words of the memories. Direct Memory Access Controller (DMAC) with table,
: means for changing the selected state of the input/output data bus of the selector in response to a pattern detection signal from the pattern detection section to perform memory switching; and updating a reference block of the reference table of the DMAC in synchronization with the memory switching. The pattern detection signal is used to switch each memory using hardware processing.

Effects The present invention uses the above-described configuration to switch between a plurality of memories by hardware processing, and therefore does not require software processing time to switch between each memory, unlike the conventional method. Therefore, there is no need for a buffer memory for absorbing fluctuations in software processing time. Therefore, high-speed data transfer can be achieved without increasing the circuit scale.

Embodiment FIG. 1 is a schematic block diagram showing an embodiment of a memory control device according to the present invention, and this embodiment shows an example of application to a car Y-7 axis.

In FIG. 1, 21 is R memory (DRAM) ~2
2 is G memory (DRAM), 23 is B memory (DRA)
In M), these JG and B memories 21, 22, and 23 are arranged in the same address space, and generally constitute a plurality of memory banks. In the following explanation, when simply referred to as memory, each of the above J(),
This includes the B memories 21, 22, and 23.

24 is an input/output data bus of the B memory 23 (hereinafter referred to as B
25 is an input/output data bus of the G memory 22 (hereinafter referred to as a G data bus), 26 is an input/output data bus of the R memory 21 (hereinafter referred to as an R data bus), and 27 is a data bus for each of these data. Bus 24, 25,
26 (each 16 bits) is selectively switched based on data in the memory and data written in the memory (described later); 28 is an input/output data bus of the selector 27;

29 is a pattern detection unit for detecting a memory switching pattern written in the memory (hereinafter referred to as a unique pattern. Details will be described later); 3o is an output signal of the detection unit 29; This becomes an input signal to the glue read/write control section 31.

32 is the read/write control signal (R ■) of the R memory 21
, 33 is a read/write control signal (GW
E), 34 is the read/write control signal (B■) of the B memory 23, 35 is the write enable signal (WE), and ■3
5 is outputted to the control bus 36.

37 is a memory refresh control unit; 38 is an address bus for inputting a memory address to the memory; 39; and 40 is a control signal (RAS) for accessing the memory.

CAS), 41 is address bus, 42 is head, RAM
43 is a microprocessor (CPU)
, 44 is a direct memory access controller (DMAC), and 45 is a data bus.

FIG. 2 shows the allocation (structure) of the internal data of the R memory 21, G memory 22, and B memory 23 arranged in the same memory address a1 space.

Inside each JG, B memory 21, 22, 23, there is a pattern for memory switching, a so-called unique pattern 721a.
, 21b, 22a, 22b, 23a
, 23b are written to the data in the memory periodically, that is, at every predetermined address.

In this example, each line (first line, second line,
...) for each JG, B memory 21, 22, 23 internal data (R component 1st line image data, R component 2nd line image data, G component 1st line image data,...) In the last part of the unique pattern 21a, 21
b, ... is written.

FIG. 3 is a time chart showing the switching timing of the memory, and in the figure, 46 is a pattern detection signal within the pattern detection section 29 that instructs the detection of the unique pattern written in the memory; corresponds to the output signal 30 of the pattern detection section 29. 47 to 49 are control signals for instructing which data bus to select from memory input/output data buses 24 to 26, 47 is a select signal for instructing to select R memo IJ21, and 48 is G memory 22.
A select signal 49 instructs to select the B memory 23;

A hatched portion in the select signal 47 indicates that the input/output data bus 24 of the R memory 21 is selected by the pattern detection signal 46 in that section. Similarly, the shaded portion in the select signal 48 corresponds to the G memory 22.
The input/output data bus 25 also receives the select signal 49.
The shaded area inside is the input/output data bus 26 of the B memory 23.
indicates that they are selected.

In short, when reading data from the memory, the selection states of the input/output data buses 24 to 26 of the memory change in each of the hatched sections according to the pattern detection signal 46 from the pattern detection section 29. In other words, memory switching is performed by pattern detection through hardware processing.

50 is data from the memory (first line data Al,
A2. A3, second line data Bl.

...) and the reference table (hereinafter referred to as link array table) 5 referred to by the DMAC 44 at that time.
1 (see FIG. 4).

The link array table 51 is provided in the DMAC 44 and is referred to when the DMAC 44 or the CPU 43 accesses the memory to transfer data.As shown in FIG.
Reference blocks AI, A2 . corresponding to A2 , A3 . A
3 and the reference blocks Bl, B2.B3 corresponding to the second line data Bl, B2°B3. It consists of reference blocks corresponding to the number of data on each line, such as B3, which are assembled for each line and arranged in series.

Each of the reference blocks AI, A2. The internal structure of...
As shown in FIG. 4, it consists of a memory address (memory transfer address), the number of transfer words (number of transfer words), and a link address.

The memory address is the address at which the DMAC 44 starts data transfer, and the number of transfer words indicates how many words are to be transferred from the memory address. be configured accordingly. Further, the link address is, for example, a pointer indicating which table's reference program should be referred to after the transfer of the reference block A1 is completed.

Here, the same memory address a1 is written in the memory addresses of the reference blocks A1 to A3.

That is, a reference block such as A (A= Al , A
2.

A memory address (for example, al) written in n consecutive reference blocks (for example, A1, A2, A
3), reference blocks that are the same and have the same memory address are successively referenced as many times as there are memories.

FIG. 5 shows the positioning of the memory control device according to the present invention within the color facsimile machine in this embodiment. In the figure, 60 is a color scanner, 61 is a color printer, 62 is a memory control device according to the invention (see FIG. 1), 63 is a communication control unit, 64 to 66 are JGs written in the memory from the color scanner 6o, B data signal, 67
69 are JG and B data signals from the memory to the color printer 61, 70 is an input/output data signal to the memory control unit 62, and 71 is an input/output data signal to the line. On the line, the signal 71 is transmitted for each R, G, and B line.

Next, the memory control device configured as described above (Fig. 1~
(see FIG. 4), its operation will be explained below.

First, when reading data from the R memory 21, G memory 22, and B memory 23, the memory address is output from the DMAC 44 to the address bus 41, and the write enable 3 is output.
5 becomes H” level. At this time, the read/write control unit 3
1 output R■32. G■733゜BWB 34 all”
becomes H" level. In other words, all memories are in a read state and the R data bus 26, G data bus 25, and B
Data at a memory address from address bus 38 is read onto data bus 24 .

The output signal 30 (pattern detection signal 46) of the pattern detection section 29 selects the R memory 21 as an initial setting. Therefore, the data on the R data bus 26 is output to the input/output data bus 28 of the selector 27.

The DMAC 44 is the link array table 51 in FIG.
The transfer operation continues while updating the memory address to be read until the transfer of the number of transfer words written in is completed.

On the other hand, the selected state of the memory does not change until the unique pattern written in the memory (see FIG. 2) is read out, and the data is transferred onto the data bus 28 while the R memory 21 is selected. Output.

When the unique pattern is read out, the pattern detection signal 46 shown in FIG. 3 is generated inside the detection unit 29, and the selector 27 output is transferred from the R memory 21 to the G memory as shown in FIG. Changes to 23. That is, the pattern detection signal 16 from the pattern detection section 29 changes the selected state of the input/output data buses 24 to 26 of the memory (in this case, the G data bus 25 is selected).At the same time, the DMAC 44 link array・
The reference to the reference block A1 of table 51 is finished, and the next reference block A2 is referenced to continue the transfer. That is, the DMAC 44 executes data transfer while updating the reference block of the link array table 51.

Since the memory address of the updated reference block A2 is the same memory address a1 as the reference block A1, transfer starts again from the same address space.

At this time, since the selector 27 is in the selected state of the G data bus 25, the R data bus 26 and the G data bus 2
5. Of the B data buses 24, only the data on the G data bus 24 is output onto the input/output data path 28 of the selector 27.

Continuing this operation, when the unique pattern written in the memory is detected, the selection state of the selector 27 changes from the G memory 22 to the B memory 23, as shown by select signals 48 and 49 in FIG.

By repeating this, the R, G, B memory 21 ~
The data of 23 is output on the input/output data path 28 of the selector 27 for each line.

During this time, the CPU 43 does not perform program processing for memory switching. In other words, hardware processing
Memory switching is performed by detecting a unique pattern written in memory. In synchronization with this, the link array table 51 of the DMAC 44 is also switched by software processing.

Next, a write operation to the memory will be explained.

During memory writing, input data is input from the input/output data bus 28 of the selector 27. The input data on the data bus 28 is transmitted to which memory data bus 2 based on the output signal 30 (pattern detection signal 46) of the pattern detection section 29.
It is decided whether to put it on numbers 4 to 26.

Here, it is assumed that the output signal 30 of the pattern detection section 29 selects the R data bus 26 as an initial setting. This memory selection signal 30 is also input to the read/write control section 31, where a control signal R32. Any one of GRE33 and BRE34 becomes "L" level.

Initially, R Memo 1J21 is selected, so borrow ■32
is at "L" level, and the others are at "H" level. Therefore, the R memory 21 is in the write state, and the other G and B memories I
J 22 and 23 are in a read state.

In this case, writing to the memory is performed with reference to the link array table 51 of FIG. 4, as in the case of reading described above.

When the pattern detection unit 29 detects a unique pattern, the unique pattern is written into the memory, and then the selection state of the selector 27 changes from the R memory selection state to the G memory selection state (== the reference block of the link array table 51 also changes). A
1 to A21 = change.

In other words, when the unique pattern is written to the memory, the memory data buses 24 to 24 of the selector 27 are
The selection state of 26 changes and memory switching is executed. At the same time, the reference blocks of the link array table 51 of the DMAC 44 are also switched and updated by software processing.

Under this state, data from the selector 27 is written to the G memory 23. Note that the switching of the link array table 51 by software processing and the switching of the memory data buses 24 to 26 by hardware processing are synchronized.

By repeatedly performing the above operations, writing to the memory is performed. The inside of the memory to which the data has been written has a data structure as shown in FIG.

As mentioned above, even when writing to memory,
As in the case of reading, the CPU 43 does not execute program processing for memory switching.

Effects of the Invention As is clear from the above explanation, the present invention switches the input/output data bus of the memory bank based on the data in the memory and the unique pattern written in the memory, so that it is possible to This eliminates the need for software processing to switch memory between memory locations, and has the effect of increasing the speed of data transfer processing without increasing the circuit scale.

[Brief explanation of drawings]

FIG. 1 is a schematic configuration block diagram showing an embodiment of a memory control device according to the present invention, FIG. 2 is a data allocation diagram showing an example of the data structure inside the memory, FIG. 3 is a memory switching timing diagram, and FIG. FIG. 4 is a structural diagram of a link array table (reference table), FIG. 5 is a block diagram showing a schematic configuration of a color facsimile to which the present invention is applied, and FIG. 6 is a block diagram showing a schematic configuration of a conventional memory control device. 7 are conceptual diagrams for explaining the processing time for memory switching. 21...R memory, 22...G memory, 23...
B memory, 21a, 21b, 22a, 22
b, 23a, 23b - Unique pattern (memory switching pattern), 24... B memory input/output data bus (B data bus), 25... G memory input/output data bus (G data bus), 26...R memory input/output data bus (R data bus), 27...Selector, 29...Pattern detection unit, 31...Read/
Write control unit, 44... Direct memory access controller (DMAC), 51... Link array table (reference table), al... Memory address (memory transfer address). Name of agent: Patent attorney Toshio Nakao (1st person, 2nd person)
7 Figure 3 Figure 4 Figure 5

Claims (1)

[Claims] a memory bank consisting of a plurality of memories in which unique patterns are written periodically in the same address space; a selector for switching input/output data buses of the plurality of memories; a direct memory access controller (D
MAC), and means for changing the selection state of the input/output data bus of the selector in response to a pattern detection signal from the pattern detection section to perform memory switching;
A memory control device comprising means for updating a reference block of a reference table of the DMAC in synchronization with the memory switching.