JPH02266452A - Device for accessing cpu bus in other system - Google Patents

Abstract

PURPOSE:To make it possible to access all of memories and I/O devices connected to the other system by executing the output control of a three-state buffer for connecting a register to a CPU bus in the other system, the acquisition control of the CPU bus in the other system and the wait control of a CPU in the self-system. CONSTITUTION:An address and a command to be accessed are previously set in registers 1, 2 by an I/O write instruction outputted from the CPU in the self-system, and at the time of writing, write data also are previously set in a register 3. The acquisition of the CPU bus in the other system, address output, data I/O, command output, and wait control are executed by a timing generator 22. Consequently, all the memories and I/O devices to be connected to the CPU bus in the other system can be accessed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention is applied to an information processing device configured with multiple CPUs. In particular, it relates to an access means for accessing a CPU bus of another system.

〔overview〕

The present invention provides a means for accessing the CPU bus of another system that temporarily holds commands, addresses, and data, and sends them to the CPU bus of the other system at a predetermined timing. It is possible to access all of the memory and devices in the system.

[Conventional technology]

In the conventional example, depending on the address, the memory of the own system or IO
A distinction is made between accessing a device and a memory connected to the CPU bus of another system or a 0 device, and directly accessing the CPU bus of another system.

[Problem that the invention seeks to solve]

In such a conventional example, access between the own system and other systems is switched by address, so the CPU of the own system cannot access all of the memory and l01i locations connected to the CPU bus of the other system. There is a drawback that it cannot be done.

The present invention aims to eliminate such drawbacks, and aims to provide a CPU bus access device for other systems that can access all of the memories and devices connected to other systems.

[Means for solving problems]

The present invention provides a memory means and input/output means which are inserted into a path between a CPU bus of its own system and a CPU bus of another system to which memory means and input/output means are connected, and which are connected to the CPU bus of the other system. A register that holds the addresses and data related to this, the write and read commands for this memory means, and the write and read commands for this input/output means, and the output of this register and the C of the other system.
Selects a three-state buffer inserted in the path to the PU bus and a predetermined three-state buffer from among these three-state buffers, and enables this three-state buffer at the timing associated with bus acquisition control and wait control. The present invention is characterized by comprising a timing generating means.

[Effect]

address, data and memory write, memory read,
Holds rO write and rO read commands, respectively.
It controls the output of the three-state buffer that connects these registers to the CPU bus of the other system, controls the acquisition of the CPU bus of the other system, and controls the wait of the CPU of the own system.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. The figure is a configuration diagram showing the configuration of this embodiment. As shown in the figure, this embodiment is inserted into a path between the CPU bus of its own system and the CPU bus of another system to which memory means and input/output means are connected, and is connected to the CPU bus of this other system. a command register 1 which is a register that holds addresses and data related to the memory means and input/output means, write and read commands for this memory means, and write and read commands for this input/output means, respectively;
, address register 2 and data register 3, and three-state buffers 5.6 and 7 inserted in the path between the output of this register and the CPU bus of the other system,
It is provided with a timing generator 22 which is a timing generating means that selects a predetermined three-state buffer from among the three-state buffers 5, 6 and 7, and enables this three-state buffer at the timing associated with bus acquisition control and wait control. .

Next, the operation of this embodiment will be explained. Command register 1 holds contents indicating whether the command for the CPU bus of the other system is memory read command 16, memory write command 17, IO read command 18, or IO write command 19. IO
Write commands in advance according to write instructions. Address register 2 holds the address of the memory or IO device connected to the CPU bus of the other system, and
■Write the address you want to access in response to the 0 write command on the U bus. Data register 3 holds the write data at the time of memory write or ■0 write, and
Write data in accordance with the 10 write command of the U bus. Selection of each register is performed by decoding address 9 with decoder 4.

The timing generator 22 makes the hold request 20 true when the data register 3 or the three-state buffer 8 is accessed, makes a hold request to the CPU of another system, and sets the wait 13 to true in order to apply a wait to the CPU of the own system. do. When the CPU of the other system issues hold permission, the hold permission 21 becomes true and the CPU bus of the other system is acquired.

After the CPU bus of another system is acquired, when writing memory or writing 0, the address enable 23 is set to true, the address is output through the three-state buffer 6, the data enable 25 is set to true, and the write data is sent through the three-state buffer 7. output, set the command enable 24 to true, output the command through the three-state buffer 5, set the wait 13 to false after a certain period of time, and write the command enable 24, data enable 25, address enable 23, and hold request 20 as false in sequence. Finish the process. Memory read or IOU
- At the time of mode, the address enable 23 is set to true, the address is output through the three-state buffer 6, the command enable 24 is set to true, the command is output through the three-state buffer 5, and after a certain period of time, the wait 13 is set to false, and the three-state buffer The read data is taken in through 8, and the command enable 24, address enable 23, and hold request 20 are sequentially set to false to complete the read process.

〔Effect of the invention〕

As explained above, the present invention sets the address and command to be accessed in advance in a register by the IO write instruction of the CPU of its own system, and also sets the write data in advance in the register at the time of writing, and It acquires the CPU bus of the system, outputs addresses, outputs data, outputs commands, and controls waits, so it can access all memory and ■0 devices connected to the CPU bus of other systems. effective.

[Brief explanation of drawings]

The figure is a configuration diagram showing the configuration of an embodiment of the present invention. 1... Command register, 2... Address register, 3... Data register, 4... Decoder, 5.6
．． 7.8... Three-state buffer, 9.14...
・Address, 10.15...Data, 11.19...
・IO write command, 12.18... ■0 read command, 13... wait, 16... memory read command, 17... memory write command, 20...
・Hold request, 21...Hold permission, 22...
Timing generator, 23...Address enable pin 24...Command enable, 25...Data enable.

Claims (1)

[Claims] 1. A memory means inserted into a path between a CPU bus of its own system and a CPU bus of another system to which memory means and input/output means are connected, and connected to the CPU bus of this other system. and a register that holds addresses and data related to the input/output means, write and read commands for this memory means, and write and read commands for this input/output means, and a register between the output of this register and the CPU bus of the other system. A three-state buffer inserted into the path; and timing generation means for selecting a predetermined three-state buffer from among the three-state buffers and enabling the three-state buffer at a timing associated with bus acquisition control and wait control. A CPU bus access device for other systems, which is characterized by: