JPH02197961A - Information processor - Google Patents

Abstract

PURPOSE:To improve the executing speed of an instruction train by transmitting a process start enable signal to a memory control part with no intervention of an instruction transmission system, etc. CONSTITUTION:A store request and a process holding request are sent to a memory control part 2 when a vector store instruction is stored in an instruction register 11. Thus the part 2 prepares for execution of a due process. Then a process start enable signal is transmitted when the data on a vector register is decided to execute the process related to the store request prepared at the part 2. At he same time, the part 2 reads data out of a memory part 3 when a load request is produced and stores the data in an internal data buffer 23. Then the data is quickly loaded to an arithmetic executing part 4 from the buffer 23 at output of a data transfer enable signal. Thus the vector load processing parallelism can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an information processing device capable of vector processing, and particularly to improvements in vector load and vector store control.

[Conventional technology]

In general, an information processing device capable of vector processing has a storage section (main memory) that stores instructions and data, an operation execution section that performs vector operations, and a system that supplies instructions from the storage section to an execution control section and connects the storage section and operation execution section. It includes a storage control unit that transfers data, and an execution instruction control unit that decodes instructions, manages resources, and controls each unit, and can process vector data at high speed using a so-called pipeline method.

The configuration and operation of a conventional information processing apparatus will now be described using as an example a case where the following vector processing command sequence is specified in a program.

VLD Vl 1M - (1) VADD
V2 ←S+V1 −(2)VST M4
-V2 ・(3) VLD V51M
・(4) VMPY V7←5xV5 ・
(5) VST M4-V7 ・
(61 Here, instruction (1) is a vector load instruction to load vector data from the storage unit into vector register v1, and instruction (2) is a scalar data S to vector data loaded to vector register v1 by instruction (1).
Instruction (3) is a vector store instruction that stores the operation result stored in vector register v2 by instruction (2) in the storage section. Instruction (4) is a storage instruction. A vector load instruction that loads vector data from the part into vector register v5, and instruction (5) is a vector that multiplies the vector data loaded into vector register ■5 by instruction 14) by scalar data S and stores the result in vector register v7. The multiplication instruction, instruction (6), is a vector store instruction that stores the operation result stored in the vector register v7 by instruction (5) in the storage section. Moreover, FIG. 3 is a time chart when the above-mentioned vector processing instruction sequence is executed by a conventional vector processing device.

The instruction order specified in the program is the above instruction (1)
In the cases of (6) to (6), instructions are stored in the instruction stack in the execution instruction control unit in order from instruction (1) and decoded.

First, when the instruction (, 1) is taken out from the instruction stack and decoded, since it is a vector load instruction, this vector load instruction is sent to the storage control unit, and the storage control unit responds by reading the instructions in the storage unit. Access is started, and the read vector data in the storage section is loaded into the vector register Vl of the arithmetic execution section. The execution instruction control unit executes the instruction (1
) is decoded, instruction (2) is decoded in parallel with the activation of instruction (1), and this instruction (2) is the same as instruction (1).
Since the instruction uses vector data loaded with
It waits for the vector data to be loaded into the vector register v1, and when the data starts to be loaded into the vector register V1, it passes the scalar data S and activates the instruction (2) to the arithmetic execution unit. As a result, the arithmetic execution unit starts the operation of adding the scalar data S to the vector data in the vector register v1 and storing the result in the vector register v2. When the calculation execution unit starts the calculation and the result is written to the vector register v2, the execution instruction control unit that was decoding the next instruction (3) stores the data in the vector register v2 at that timing. The instruction (3) to store in the section is sent to the storage control section. When the storage control unit receives and decodes this instruction (3),
The operation of storing the data of vector register v2 in the storage section is started. The execution instruction control unit decodes the instruction (4) after decoding the instruction (3), but the instruction (4) is an instruction to load the data in the storage unit into the vector register v5, and at that point, the third As shown in the time chart of the figure, since the storage unit is accessed by the vector store processing by instruction (3), execution of instruction (4) is delayed until the processing of instruction (3) is completed. Then, after the necessary rendezvous, instruction (4) is executed, and then instruction (5)
, instruction (6) is processed in the same way as instructions (2) and (3).

[Problem to be solved by the invention]

As mentioned above, in conventional information processing devices, the next instruction to be executed taken out from the instruction stack is the instruction 1), (4
), these instructions are sent to the storage control unit at the timing when they can actually be processed.
The storage control section is configured to access the storage section for the first time and supply the read data to the arithmetic execution section. Therefore, if the absolute time required for the storage control unit to access vector data in the storage unit is long, the performance of the information processing device will deteriorate. In particular, like the instruction sequence mentioned above,
In an instruction example that includes a preceding vector store instruction (3) and a subsequent vector load instruction (4), there are many cases in which the two use different storage areas, and therefore the subsequent vector load instruction (4) There is no problem with accessing the storage section before the preceding vector store instruction, but conventional information processing bags! In this case, instruction execution instructions are actually sent in the order specified in the program, so the execution of the subsequent vector load instruction (4) waits until the access to the storage section of the preceding vector store instruction (3) is completed. As a result, there are many inactive states in the usage status of the storage unit by the storage control unit, and the storage unit is not used efficiently.
As a result, the program execution time becomes longer.

Regarding vector store instructions, conventionally a configuration has been adopted in which the vector store instruction is sent to the storage control unit when the data to be stored is ready, that is, when resources become available. It takes some time for the storage control section to start executing the command, depending on the instruction transmission system and the decoding of the instructions within the storage control section.

Therefore, it takes a long time from when the resource becomes available until the store process starts.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide an information processing device that can improve the execution speed of an instruction sequence including vector load instructions and vector store instructions.

[Means to solve the problem]

In order to achieve the above object, the present invention provides a storage unit that stores data, an operation execution unit that performs vector operations, a storage control unit that controls data transfer between the storage unit and the operation execution unit, and instructions to be executed. An information processing device including an execution instruction control unit that has an instruction stack for temporarily storing instructions, decodes instructions, manages resources of the operation execution unit, etc., and sends control information to the storage control unit and the operation execution unit. Stores the instruction stored in the register in the instruction stack, decodes the instruction, sends a store request and processing standby request to the storage control unit if it is a vector store instruction, and sends a store request and a processing wait request to the storage control unit if it is a vector load instruction. a first control means that sends a load request to the storage control unit when a conflicting vector store instruction is not stored in the instruction stack; The arithmetic execution unit sends a processing start enable signal to the storage control unit at a timing when there is no conflict for resources related to the store, and when the instruction is a vector load instruction, the arithmetic execution unit sends a resource conflict related to the load. the execution instruction control section includes a second control means for sending a data transfer enable signal to the storage control section at a timing when the storage control section does not occur, and the first storage control section temporarily stores data from the storage section. The arithmetic execution unit has a buffer, and prepares to execute the process related to the store request in response to the store request and the processing standby request, and prepares to execute the process related to the store request prepared to execute in response to the process start enable signal. transfers data from the storage unit to the storage unit, reads data from the storage unit to the buffer in response to the load request, reads data from the buffer in response to the data transfer enable signal, and reads the data from the buffer, and the operation execution unit It has a configuration that sends data to

(Function) The information processing device of the present invention has an instruction stack that temporarily stores instructions to be executed, decodes instructions, manages resources of the operation execution unit, etc., and sends control information to the storage control unit and the operation execution unit. A first control means provided in the execution instruction control unit stores the instruction stored in the instruction register in the instruction stack, decodes the instruction, and, if the instruction is a vector store instruction, executes the instructions related to the vector store instruction. A store request and a processing standby request are sent to the storage control unit, and if it is a vector load instruction, a load request is sent to the storage control unit because a vector store instruction that conflicts with the vector load instruction is not stored in the instruction stack. However, a second control means, which is also provided for execution instruction control, decodes the first instruction of the instruction stack and, if it is a vector store instruction, stores it in the arithmetic execution unit at a timing that does not cause contention for resources related to the store. It sends a processing start enable signal to the control unit, and when it is a vector load instruction, it sends a data transfer enable signal to the storage control unit at a timing that does not cause resource contention for the load in the arithmetic execution unit.

On the other hand, in response to the store request and the process standby request, the storage control unit prepares to execute the process related to the store request, and in response to the process start enable signal, the storage control unit performs storage from the arithmetic execution unit related to the store request prepared for execution. In response to a load request, data is read from the storage unit and temporarily stored in the buffer, and in response to a subsequent data transfer enable signal, the data is read from the buffer and sent to the calculation execution unit. .

〔Example〕

Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of essential parts of an embodiment of an information processing apparatus to which the present invention is applied. The information processing apparatus of this embodiment includes an execution instruction control section 1, a storage control section 2, a storage section 3, and an arithmetic execution section 4.

The storage unit 3 is composed of a main memory and the like, and stores data, instructions, and the like. The calculation execution unit 4 has a vector register, a vector calculation unit, etc., and is a part that executes vector calculations and the like instructed by the execution instruction control unit 1. The execution instruction control unit l decodes instructions.

This is a part that outputs control information to the storage control unit 2 and the arithmetic execution unit 4 in order to manage resources and execute a sequence of instructions specified in a program, and the instruction register 11.
Instruction stack 12. Decoder 13, address check circuit 14. Decoding/R match check circuit 15. It includes a resource status management circuit 16. The storage control unit 2 is a part that controls data transfer between the storage unit 3 and the calculation execution unit 4,
Control circuit 21. Store instruction stack 22. It includes a data buffer 23.

Each component in the execution instruction control unit 1 has the following functions.

- Instruction register 11 Holds instructions fetched from the storage unit 3 via a bus (not shown).

・Decoder 13 Transfers the instructions held in the instruction register 11 to the instruction stack 12
At the same time, it decodes the instruction, and if it is a vector store instruction, it sends a store request including the address information of the storage section 3 used by the instruction and a processing standby request to the storage control section 2, and if it is a vector load instruction, For example, when a vector store instruction exists in the instruction stack 12, the address range of the storage unit 3 accessed by the vector store instruction is compared with the address range of the storage unit 3 accessed by the current vector load instruction, and both are compared. Based on the detection result of the address check circuit 14 which detects whether or not there is a conflict, a load request containing the address information of the memory unit 3 used by the vector load instruction is sent to the memory control unit 2 only when there is no conflict. Send out.

・Instruction stack 12 The instructions sent from the decoder 13 are temporarily stored.

・Address check circuit 14 When the decoder 13 decodes the instruction stored in the instruction register 11 as a vector load instruction, if a vector store instruction exists in the instruction stack 12, it is accessed by that vector store instruction. Address range of storage unit 3 and storage unit 3 accessed by this vector load instruction
A conflict between the two is detected by comparing the address range of the two.

Note that the address range of the storage unit 3 accessed by a vector store instruction and a vector load instruction is determined based on the vector store/load start address, the distance between vector store/load elements, and the number of vector store/load elements of each instruction.

-Resource status management circuit 16 This circuit manages the current status of various resources such as vector registers in the arithmetic execution unit 4 based on information provided from each unit.

・Decoding/IL1 check circuit 15 Deciphers the first instruction of the instruction stack 12, performs a conflict check against the state indicated by the resource state management circuit 16, and sends control information to the storage control unit 2 and the arithmetic execution unit 4. . Specifically, the following operations are performed.

When the first instruction of the instruction stack 12 is a vector store instruction, a processing start enable signal is sent to the storage control unit 2 when the vector register to be stored is not being read by a preceding instruction or writing has not yet started. do.

When the first instruction of the instruction stack 12 is a vector load instruction, if the vector register to be loaded is not being written to by the preceding instruction, or if reading has started, a data transfer enable signal is sent to the storage control unit 2. Send.

If the first instruction of the instruction stack 12 is an arithmetic instruction, the contention of resources related to the arithmetic operation and the preparation status of the arithmetic data are checked, and if there is no problem, an execution instruction is sent to the arithmetic execution unit 4.

Further, each component in the storage control unit 2 has the following functions.

・Data buffer 23 The data read from the storage unit 3 is temporarily stored.

This stored data is sent to the calculation execution section 4.

・Control circuit 21 Receives various information sent from the execution instruction control unit 1,
Each unit is controlled so that the storage control unit 2 executes the corresponding operation. Specifically, the following operations are performed.

Upon receiving a store request and a processing standby request, the store request is stored in the store instruction stack 22,
Later, by receiving a processing start enable signal, the store request stored in the store instruction stack 22 is activated to access the storage unit 3, and the data in the vector register in the arithmetic execution unit 4 is stored in the storage unit 3. This is notified to the resource status management circuit 16 of the execution instruction control unit 1.

When a load request is received, the storage unit 3 is accessed and vector data is stored in the data buffer 23, and when a data transfer enable signal is received later, the corresponding data begins to enter the data buffer 23 or is already stored in the buffer. If so, it starts sending the data in the data buffer 23 to the vector register of the arithmetic execution section 4, and also notifies the resource state management circuit 16 of the execution instruction control section 1 of this fact.

Figure 2 shows the following instruction sequence, VLD, used in explaining the conventional example.
Vl ←M − (1) VADD V2
←S+V 1...(2) VST M-V
2 ・(3) VLD V5←M
...(4) V M P Y V 7 ← S X V
5 - (51V STM-V 7
- (6) is a time chart when processed by the information processing device of FIG. 1. The operation of the embodiment shown in FIG. 1 will be described below with reference to the time chart shown in FIG.

When the vector load instruction (1) is stored in the instruction register 11, the decoder 13 detects that since there is no preceding vector store instruction in the instruction stack 12, the check result of the address check circuit 14 is that there is no address conflict, and the memory control is performed. The storage control unit 2, which issues a load request to the storage unit 2, starts the process of reading data from the storage unit 3 into the data buffer 23 by receiving this load request. When the vector load instruction (1) is stored in the instruction stack 12 and then the vector addition instruction (2) is decoded by the decoder 13, it is stored in the instruction stack 12 and the next instruction (3) is decoded. Ru. Since instruction (3) is a vector store instruction, the decoder 13 sends a store request and a processing standby request to the storage control unit 2, and the storage control unit 2 receives and decodes it, and adds the store request to the store instruction stack. Next, the vector load instruction (4) is decoded in the decoder 13. Now, assuming that the address range of the storage unit 3 accessed by the vector load instruction (4) and the address range of the storage unit 3 accessed by the preceding vector store instruction (3) do not overlap, no conflict occurs in the address check circuit. 14, the decoder 13 issues a load request to the storage control unit 2, and the storage control unit 2 receives this, thereby
End of access to the storage unit 2 by the preceding instruction (1) Immediately starts the process of reading data from the storage unit 3 into the data buffer 23 When the 0-order vector multiplication instruction (5) is decoded by the decoder 13 , are stored in the instruction stack 12, and then when the vector store instruction (6) is decoded, the decoder 13 sends a store request and a processing standby request to the storage control unit 2. stores the store request in the store instruction stack 22.Instructions (1) to (6) are stored in the instruction stack 1 as shown in 0 or above.
In the storage control unit 2, the data to be loaded with the vector load instruction (1) is stored from the storage unit 3 into the data buffer 23, and subsequently the data to be loaded with the vector load instruction (4) is stored in the storage unit 2. 3, the data is stored in the data buffer 23.

On the other hand, the instructions stored in the instruction stack 12 are processed by the decoding/conflict check circuit 15 in order from the first instruction (1). When the decoding/conflict check circuit 15 decodes the instruction (1) and identifies that it is a vector load instruction, it checks whether the load destination vector register v1 can be used or not according to information from the resource status management circuit 16. When it is available, a data transfer enable signal is sent to the storage control unit 2. Upon receiving this data transfer enable signal, the storage control unit 2 starts the operation of transferring the data to the vector register v1 of the arithmetic execution unit 4 when the corresponding data begins to enter the data buffer 23.

After processing the instruction (1), the decoding/conflict check circuit 15 decodes the next leading instruction (2), and since this is a vector addition instruction that uses the vector register Vl, the memory control unit 2 The data is loaded into the vector register Vl, the state related to the vector register Vl in the resource state management circuit 16 is updated, and when it is recognized that the data is prepared in the vector register V1, the instruction (2) is activated. The execution instruction is sent to the calculation execution unit 4.
Send to. As a result, the calculation execution unit 4 executes the instruction (2).
The vector addition operation is started and the result is stored in the vector register (2).

When the instruction (2) is started, the decoding/conflict check circuit 15 checks whether the data to be stored has been prepared in the vector register 2 since the next instruction (3) is a vector store instruction. 16, and sends a processing start enable signal to the storage control section 2 at the timing of completion of preparation. When the storage control unit 2 receives this process start enable signal, it stores the store instruction stack 22
The corresponding store request stored in is activated, and the data in vector register v2 is stored in storage unit 3.

Next, the decoding/conflict check circuit 15 decodes instruction (4). Since this instruction (4) is a vector load instruction, it sends a data transfer enable signal to the storage control unit 2 at the timing when the load destination vector register v5 is available. When the storage system i11 unit 2 receives this data transfer enable signal, it starts the process of transferring data to the vector register v5 of the arithmetic execution unit 4, but as is clear from the time chart of FIG. Since most of the data to be transferred in response to the request has already been stored in the data buffer 23, data transfer is started immediately and the necessary data is promptly stored in the vector register 5.

Thereafter, the decoding/conflict check circuit 15 reads the instruction stack 1.
Instruction (5) and instruction (6) in 2 are changed to instruction (2) and instruction (3).
), and the execution control of the above instruction sequence is completed. As is clear from a comparison of the time charts of FIGS. 2 and 3, in this embodiment, the instruction sequence of instructions (1) to (6) can be executed at high speed.

〔Effect of the invention〕

As explained above, in the information processing device of the present invention,
When the vector store instruction is stored in the instruction register, a store request and a processing standby request are sent to the storage control unit to make the storage control unit prepare for execution, and processing starts when the data in the vector register is determined. It sends out a ready signal to perform the processing related to the store request that has been prepared for execution within the storage control unit, and the time required for command transmission system and instruction decoding within the storage control unit is absorbed by the preceding processing, and the processing can be started. Since the signal is quickly transmitted to the storage control unit without going through the command transmission system, etc., the time from the time when the data to be stored is ready in the vector register to the time when data storage actually starts is shortened. becomes possible.

Also, when the vector load instruction is stored in the instruction register, it is decoded and, if possible, a load request is sent to the storage control unit as early as possible, and when the data can be loaded into the vector register. A data transfer enable signal is sent to the storage control unit, and on the other hand, when a load request is issued, the storage control unit reads data from the memory unit and stores it in an internal buffer, and when the data transfer enable signal is issued. Since the data is quickly loaded from the buffer to the arithmetic control unit, the parallelism of vector load processing can be increased.

As a result of the above, according to the present invention, the execution speed of an instruction sequence including a vector load instruction and a vector store instruction can be improved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of essential parts of an embodiment of the present invention, FIG. 2 is a time chart of the embodiment of the present invention, and FIG. 3 is a time chart of a conventional example. In the figure, 1...Execution instruction control unit 11...Instruction register 12...Instruction stack 13...Decoder 14...Address check circuit 15...Decoder/conflict check circuit 16...Resource State management circuit 2...Storage control unit 21...Control circuit 22...Store instruction stack 23...Data buffer 3...Storage unit 4...Arithmetic execution unit Patent applicant: Kofu NEC Co., Ltd.

Claims (1)

[Claims] A storage unit that stores data, an operation execution unit that performs vector operations, a storage control unit that controls data transfer between the storage unit and the operation execution unit, and an instruction stack that temporarily stores instructions to be executed, and decodes instructions. , an information processing device including an execution instruction control section that manages resources of the operation execution section and sends control information to the storage control section and the operation execution section, the execution instruction control section is configured to control the execution instructions stored in the instruction register. Stores an instruction in the instruction stack and decodes the instruction; if it is a vector store instruction, sends a store request and a processing wait request to the storage control unit; and if it is a vector load instruction, sends a conflicting vector store instruction a first control means that sends a load request to the storage control unit when the instruction is not stored in the instruction stack; A processing start signal is sent to the storage control unit at a timing when no resource conflict occurs regarding the store, and when the instruction is a vector load instruction, a processing start signal is sent to the storage control unit at a timing when no resource conflict related to the load occurs in the arithmetic execution unit. a second control means for sending a data transfer enable signal to the storage control unit; the storage control unit has a buffer for temporarily storing data from the storage unit; In response to the request, preparations are made to execute the process related to the store request, and in response to the process start enable signal, data is transferred from the arithmetic execution unit to the storage unit related to the store request prepared for execution. , characterized in that it has a configuration that reads data from the storage unit into the buffer in response to the load request, and reads data from the buffer in response to the data transfer enable signal and sends it to the arithmetic execution unit. Information processing device.