JPH02263248A - Memory device - Google Patents

Abstract

PURPOSE:To start the process of the next access request before the end of the preceding access action and to access speedily by dividing a storage part into plural partial memories and adding the memory controllers which are started by the address coincidence signals received from the address decoders and work independently of each other to those partial memories respectively. CONSTITUTION:A storage part 3 is divided into partial memories 3a and 3b, and the memory controllers 4a and 4b which are started by the address coincidence signals received from the address decoders 12a and 12b and work independently of each other are added to the parts 3a and 3b respectively. Thus the controllers 4a and 4b are added to different memory parts 3a and 3b and work independently of each other. Then both memories 3a and 3b receive accesses and the internal writing cycles are started to the memories 3a and 3b only when the decoders 12a and 12b connected to the controllers 4a and 4b detect the coincidence of addresses. Thus no waiting time is produced despite the continuous connection of memory accesses. Then the memory access is attained at a higher speed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory device used in a microprocessor system.

[Conventional technology]

FIG. 4 is a block diagram showing a conventional memory device shown in the specification and drawings attached to the application of Utility Model Application No. 62-177477, for example. In the figure, 1 is a memory device, and 2 is a central processing unit (hereinafter referred to as CPU) to which this memory device 1 is connected. 3 is this memory device 1
4 is a memory controller in the memory device 1 that controls operation of memory access to the storage unit 3; 5;
is a data buffer in which data to be read and written to the storage unit 3 is latched, 6 is a memory control line through which a control signal output from the memory controller 4 to the storage unit 3 is transmitted, and T is a connection between the storage unit 3 and the data buffer. This is an internal data line through which data exchanged with the 5 is transmitted.

Further, 8 is a control signal line that transmits a control signal from the CPU 2 to the memory controller 4 of the memory device 1, 9 is a response signal line that transmits a response signal from the memory controller 4 to the CPU 2, and 10 is a control signal line that transmits a control signal from the CPU 2 to the memory controller 4 of the memory device 1. This is a data line through which data exchanged with the data buffer 5 is transmitted.

Next, the operation will be explained. Here, FIG. 5 is a timing diagram showing the write access operation.

The memory write request signal from the CPU 2 is input to the memory controller 4 of the memory device 1 through the control signal line 8, and the memory controller 4 that receives the signal makes the internal cycle start signal significant and starts an internal write cycle.

When this internal cycle start signal becomes significant, the memory controller 4 latches the write data output from the CPU 2 onto the data line 10 into the data buffer 5,
At the same time, a response signal is generated and sent to the CPU via the response signal line 9.
, 2.

Thereafter, the memory controller 4 generates a memory write signal at a predetermined timing and sends it to the storage section 3 via the memory control line 6. In response to this memory write signal, the storage section 3 receives the write data latched in the data buffer 5 via the internal data line 7, and stores it at a predetermined address. When the series of memory write access operations is completed, the memory controller 4 makes the internal cycle start signal inactive and ends the operation.

Note that if a new memory write request signal is sent from the CPU 2 before the previous internal write cycle ends, the memory controller 4 will not process the write request that occurred later until the previous internal write cycle ends. Keep me waiting,
When the previous internal write cycle ends and the internal cycle start signal becomes invalid, the next write cycle is started.

[Problem to be solved by the invention]

Conventional memory devices are configured as described above, so
If the next memory write request occurs before the internal write cycle of the storage unit 3 ends, there is a problem that the next memory access will have to wait until the previous internal write cycle ends.

This invention was made in order to solve the above-mentioned problems, and aims to provide a memory device that allows faster memory access without having to wait even when memory access occurs continuously. purpose.

[Means to solve the problem]

In the memory device according to the present invention, a storage section is divided into a plurality of partial memories, and a memory controller that is activated by an address match signal from an address decoder and operates independently of each other is individually added to each partial memory. be.

[For production]

Each memory controller in this invention is attached to a different partial memory and operates independently of each other, and only when the associated partial memory is accessed and the connected address decoder detects an address match. , starts an internal write cycle for the corresponding partial memory.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, 1 is a memory device, 2 is a CPU, 3 is a storage section, 8 is a control signal line, 9 is a response signal line, and 10 is a data line, and these are conventional ones with the same symbols as in FIG. The detailed explanation will be omitted as it is the same or equivalent part.

3a and 3b are partial memories obtained by dividing the storage section 3 into two according to addresses or memory types. 4a
, 4b are these partial memos IJ3a.

Conventional memory controller 4 provided corresponding to 3b
It is a memory controller equivalent to 5a.

5b is also a data buffer equivalent to the conventional data buffer 5 provided corresponding to each partial memo IJ3a, 3b. 5a and 5b are memory controllers 4a,
4b is a memory control line through which control signals output to the partial memories 3a and 3b are transmitted, and 7a+7b is an internal line through which data exchanged between the partial memories 3a and 3b and the data buffers 5a and 5b is transmitted. It is a data line.

11 is an address line through which an address signal given from the CPU 2 to the memory device 1 is transmitted. 12a,
12b indicates the address signal received via this address line 11 and the partial memory 3 to which it is associated.
This is an address decoder that compares the addresses a and 3b and outputs an address match signal when a match is detected. 1
3a.

Reference numeral 13b transmits the address match signals from the address decoders 12a and 12b to the memory controller 4a.

This is an address match signal line sent to 4b. Reference numeral 14 denotes an OR gate that transmits response signals from the memory controllers 4a and 4b to the response signal line 9.

Further, FIG. 2 shows the address decoder 12a.

12b is a block diagram showing the configuration of 12b. In the figure, 2
0 is an address-number setting register where address-number setting data is stored according to the setting data, 21 is an address match mask register where address match mask data is stored according to the setting data, and 22 is a register sent from the CPU 2 through the address line 11. This is an address comparison section that collectively compares the received address signal and the outputs from the address number setting register 20 and the address match mask register 21 for each bit. Here, the bit width of the address match mask register 21 is equal to the bit width of the address line 110.
This is set to be the same as the bit width, and each line of the address line 11 corresponding to a high level of each data bit of this address matching mask register 21 is unconditionally matched. Only when the results of comparing and masking each line of the address line 11 match on all lines, the address match signal line 13a (13b)
An address match signal is sent out.

Next, the operation will be explained. Here, FIG. 3 is a timing diagram showing the operation when memory write requests are generated successively to the partial memories 3a and 3b.

A memory write request signal from the CPU 2 is input to the memory controllers 4a and 4b of the memory device 1 via the control signal line 8. Also, the #1 address signal from the CPU 2 is sent to the address decoder 12 via the address line 11.
a and 12b, and a match is detected. In the case of FIG. 3, the #1 address signal is sent to the address decoder 12a.
A match is detected at , and an address match signal is output to the memory controller 4a from the address match signal 113a.

The memory controller 4a is activated by this address match signal, makes the internal cycle start signal significant, and starts an internal write cycle.

When this internal cycle start signal becomes significant, the memory controller 4a transfers the #1 write data output from the CPU 2 onto the data line 10 to the data buffer 5a.
At the same time, a response signal is output to the response signal line 9 via the OR gate 14 and sent back to the CPU 2. Thereafter, the memory controller 4a generates a memory write signal for the partial memory 3a, and sends it to the partial memory 3a via the memory control line 6a. In response to this memory write signal, the partial memory IJ 3 a takes in the #1 write data latched in the data buffer 5a via the internal data line 7a, and stores it at the address specified by the #1 address signal. When the series of memory write access operations is completed, the memory controller 4a makes the internal cycle start signal inadvertent and ends the operation.

On the other hand, when the CPU 2 receives the response signal, it starts the next access operation. Therefore, as shown in FIG. 3, regardless of whether or not the previous internal write cycle has been completed in the memory controller 4a, the CPU 2 sends a new memory write request signal and #2 address signal to the memory of the memory device 1. Controllers 4a, 4b and address decoder 1
Continuously input to 2a and 12b. In the example shown, #2
A match of the address signals is detected by the address decoder 12b, and the address match signal is outputted from the address match signal line 13b to the memory controller 4b.

The memory controller 4b is activated by this address match signal and makes the internal cycle start signal significant.

Here, since this memory controller 4b operates completely independently of the memory controller 4a, even if the memory controller 4a is in the memory write access operation, if the internal cycle start signal becomes significant, the CPU 2
#2 write data from is latched into the data buffer 5b and sent back to the CPU 2 as a response signal. After that, the memory controller 4b sends a memory write signal to the partial memory 3b, and writes the memory 4 latched in the data buffer 5b.
The #2 write data is stored in the address specified by the #2 address signal of the partial memory 3b. When the series of memory write access operations is completed, the memory controller 4b makes the internal cycle start signal inadvertent and ends the □ operation.

Here, since the address decoders 12a and 12b are configured as described above, the address matching pattern can be freely changed by specifying setting data from the outside (for example, the CPU 2). 30
It becomes possible to freely select the division method. In this way, by selecting an appropriate partitioning method depending on the system or switch, the high speed performance of the memory device can be improved.

In the above embodiment, the storage section is divided into two parts depending on the address or memory type, but it may be divided into three parts or more.The larger the number of divisions, the shorter the waiting time after a write access operation. The probability of occurrence is reduced, and faster memory access is possible.

Furthermore, in the above embodiment, a case was explained in which a data buffer was added to each partial memory, but if one of the partial memories is a high-speed memory element, the same effect can be obtained even without the data buffer. It is possible to reduce the number of parts and simplify the memory controller.

〔Effect of the invention〕

As described above, according to the present invention, a storage section is divided into a plurality of partial memories, and a memory controller that is activated by an address match signal from an address decoder and operates independently of each other is added to each partial memory. Because of this configuration, even if access requests occur consecutively, processing of the next access request can be started without waiting for the completion of the previous access operation, which has the effect of providing a memory device that can perform high-speed access. .

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a memory device according to an embodiment of the present invention, FIG. 2 is a block diagram showing the configuration of its address decoder, FIG. 3 is a timing diagram showing the write access operation of this embodiment, and FIG. The figure is a block diagram showing a conventional memory device, and FIG. 5 is a timing diagram showing its write access operation. 1 is a memory device, 2 is a CPU, 3 is a storage unit, 3a, 3b
is a partial memory, 4.4a and 4b are memory controllers,
5, 5a and 5b are data buffers, and 12a and 12b are address decoders. In addition, the same symbols in the figures indicate the same or equivalent parts. Figure 3 12af12bl Figure Figure

Claims (1)

[Claims] In accordance with a write access from the central processing unit, the data buffer latches the write data sent from the central processing unit, and at the same time sends a response signal back to the central processing unit, and then starts an internal write cycle to the storage unit. In a memory device equipped with a memory controller that prohibits the next memory access until the write cycle is completed, the storage section is divided into a plurality of partial memories based on addresses or memory types, and each of the partial memories is The memory controllers each receive an address matching signal and operate independently from each other, and each of the memory controllers receives an address sent from the central processing unit and the partial memory to which it is associated. 1. A memory device comprising: an address decoder connected to the address decoder for comparing the address with the address and outputting the address matching signal.