JP2008083762A - Microcomputer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a microcomputer that enhances the efficiency of a data transfer process for block data whose data length to be transferred is not predetermined. <P>SOLUTION: The microcomputer 10 includes: an execution control part 101 for decoding instructions; an ALU 704 for executing arithmetic processes based on the results of decoding instructions by the execution control part 101; a general-purpose register file 703; and a detection circuit 110 for detecting whether or not the data stored in the general-purpose register file 703 has a predetermined identification code (NULL character), according to the execution by the ALU 704 of a data transfer instruction between the general-purpose register 703 and a data memory 72. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a microcomputer, and more particularly to a technique for executing data transfer processing of block data whose data length to be transferred is not determined in advance by the microcomputer.

  2. Description of the Related Art Conventionally, microcomputers that are used in connection with one or a plurality of memory devices are known. An example of the configuration of the main part of a conventional microcomputer 70 is shown in FIG. A microcomputer 70 shown in FIG. 7 is connected to an instruction memory 71 and a data memory 72 via an address bus 73 and a data bus 74. The instruction memory 71 is a memory that stores an instruction sequence executed by the microcomputer 70. The data memory 72 is a memory for storing data input to the microcomputer 70 and data processed by the microcomputer 70. In FIG. 7, an instruction memory 71 and a data memory 72, which are logical structural units, are shown. These are configured by ROM (Read Only Memory), RAM (Random Access Memory), or a combination thereof. The

  The execution control unit 701 fetches an instruction from the instruction memory 71 and decodes the fetched instruction. More specifically, the execution control unit 701 determines the instruction type of the fetched instruction, acquires an instruction operand, and according to the information obtained by instruction decoding, a program counter (PC) 702 described later. The data and / or control signals are output to the general-purpose register file 703, the arithmetic logic unit (ALU) 704, the selector 707, and the selector 709.

  The program counter 702 is a register that holds an address where an instruction to be fetched by the execution control unit 701 is stored. The value of the program counter 702 is updated by the execution control unit 701. If instructions are executed sequentially, the value of the program counter 702 is updated by a value corresponding to the instruction length, but if a branch instruction is present, it is updated discontinuously with the address indicating the branch destination instruction.

  The general-purpose register file 703 has 16 general-purpose registers R0 to R15. Each of the general purpose registers R0 to R15 is an 8-bit register. The general purpose registers R0 to R15 can be used for various purposes such as using the ALU 704 as input data and output data storage locations, and using the register indirect addressing mode as a base address or index value storage location. A group of registers.

  At least the pair of registers R0 and R1, the pair of R2 and R3, the pair of R12 and R13, and the pair of R14 and R15 can be used as a 16-bit register by the pair of these 8-bit registers. These general-purpose registers are given different names for the convenience of register designation in the instruction operands in assembly language. Specifically, the register R0 is the X register, the register R1 is the A register, the register R2 is the C register, the register R3 is the B register, the register R12 is the E register, the register R13 is the D register, the register R14 is the L register, and the register R15 is the register R15. It is also called an H register.

  The ALU 704 is an arithmetic unit that performs an operation according to the instruction decode result by the execution control unit 701, and executes arithmetic operation (addition / subtraction) and logical operations such as logical sum, logical product, and exclusive logical sum. In FIG. 7, the data input to the ALU 704 and the data output after the calculation by the ALU 704 are all performed with the general-purpose register file 703. The data input source register and output destination register of the ALU 704 are determined by the execution control unit 701 based on the operand of the instruction.

  The zero determination circuit 705 is a circuit that determines whether or not the arithmetic operation result by the ALU 704 is zero and outputs a 1-bit logic signal according to the determination result. The zero determination circuit 705 outputs “1” when the calculation result by the ALU 704 is zero, and outputs “0” when the calculation result is not zero.

  A zero flag (Z flag) 706 is a 1-bit register that holds a determination result by the zero determination circuit 705.

  The selector 707 is a 2-input 1-output selector circuit. Selection of the input port of the selector 707 is performed according to a control signal output from the execution control unit 701. Specifically, when the execution control unit 701 decodes an arithmetic operation instruction and causes the ALU 704 to execute an arithmetic operation, the input terminal on the zero determination circuit 705 side is selected. On the other hand, when the ALU 704 performs other calculations, the other input terminal is selected.

  A carry flag (CY flag) 708 is a 1-bit register provided for storing a carry generated by an addition operation by the ALU 704 and a borrow generated by a subtraction operation.

  The selector 709 is a 2-input 1-output selector circuit. Selection of an input port of the selector 709 is performed according to a control signal output from the execution control unit 701. Specifically, when the execution control unit 701 decodes an arithmetic operation instruction and causes the ALU 704 to execute an arithmetic operation, a terminal for inputting a carry / borrow signal indicating the occurrence of carry and borrow in the ALU 704 is selected, and the ALU 704 is selected. The other input terminal is selected when other calculations are performed.

One of the processes executed by the microcomputer 70 is a process of transferring or copying data stored in a storage area of the data memory 72 to another storage area specified by a different address. In this specification, such a process for transferring or copying data is generically referred to as “data transfer process”. For example, Patent Document 1 discloses a microcomputer that executes data transfer processing of block data having a known data length.
JP-A 64-58039

  When the data length of the block data to be transferred is known as in the data transfer process disclosed in Patent Document 1, the data length of the block data to be transferred is first stored in a general-purpose register (for example, register R2). In addition, every time data is transferred, the value of the register R2 is decremented according to the transferred data length, and the data is transferred until the value of the register R2 becomes zero. By such data transfer processing, block data can be efficiently transferred or copied.

  However, when the data length of the block data to be transferred is not determined in advance, for example, when transferring character string data, it is necessary to determine the end position of the block data based on the contents of the transferred data. That is, the end of the data transfer process must be determined by detecting some end code indicating the end position of the block data from the transferred data string. For example, when transferring character string data, the end position of the character string data to be transferred can be detected by detecting a NULL character indicating the end position of the character string as the end code.

  Thus, when performing data transfer processing for character string data or the like whose data length to be transferred is not determined in advance, a comparison operation for determining whether or not the transferred data matches a predetermined end code Must be executed repeatedly. For this reason, there is a problem that the processing efficiency of the data transfer processing deteriorates. Note that block data and character string data for which the data length to be transferred is not determined in advance are referred to as undetermined block data and undetermined character string data in this specification, respectively.

  A specific example in which the above problem occurs will be described with reference to the programs shown in FIGS. FIGS. 8A and 8B are examples of a program in which data transfer processing of unconfirmed character string data is described in assembly language. FIG. 8A shows a program example in which the data transfer process is described by a loop process that repeats data transfer in units of 1 byte.

  The first line in FIG. 8A is a simple comment line. The MOV instruction on the second line in FIG. 8A is a data transfer instruction, the first operand indicates the data transfer destination, and the second operand indicates the data transfer source. More specifically, the instruction on the second line represented by the mnemonic “MOV A, [DE]” is one byte data from the storage area of the data memory 72 specified by the 16-bit address stored in the DE register. Is read and stored in the A register. Here, the DE register means a 16-bit register having a pair of a D register and an E register.

  The MOV instruction on the third line in FIG. 8A indicates a process for transferring the data stored in the A register to the storage area of the data memory 72 specified by the 16-bit address stored in the HL register. ing.

  The CMP0 instruction on the fourth line in FIG. 8A is a comparison instruction for determining whether the 8-bit data stored in the A register is “0x00”. Since “0x00” is used for the NULL character, this command is a command for determining whether the data acquired from the data memory 72 is a NULL character. More specifically, an operation for subtracting 0 from the data stored in the A register is executed by the instruction on the fourth line represented by the mnemonic “COMP0 A”, and when the operation result is zero, the Z flag 706 is set. “1” is set.

  The INCW instruction on the fifth line in FIG. 8A is an instruction for incrementing the DE register that stores the data transfer source address. Also, the INCW instruction on the sixth line in FIG. 8A is an instruction for incrementing the HL register for storing the data transfer destination address. Finally, the BNZ instruction on the seventh line in FIG. 8A is a conditional branch instruction that branches to the first line when the Z flag 706 is set to “0”.

  As shown in FIG. 8A, in the data transfer of the undetermined character string data, it is necessary to repeatedly execute a comparison instruction (CMP0 instruction) for detecting a NULL character indicating the end of the character string data. For this reason, the efficiency of the data transfer process is deteriorated by the time consumed for the repeated execution of the comparison instruction.

  On the other hand, FIG. 8B is a program example in which the loop expansion is advanced as compared with FIG. 8A, and is a program example in which the data transfer process is described by a loop process that repeats data transfer in units of 4 bytes. 8B describes data transfer from the data memory 72 to the general-purpose register file 703 using a data transfer instruction (MOVW instruction) in units of 2 bytes. The MOVW instruction on the second line in FIG. 8B reads 2-byte data from the storage area of the data memory 72 designated by the address obtained by adding the offset value “0” to the stored value of the DE register and stores it in the AX register. The transfer process to be performed is shown. The process of storing the 2-byte data read by the MOVW instruction on the second line in the transfer destination memory area is completed from the MOV instruction on the third line to the BZ instruction on the eighth line. However, two comparison instructions (the fourth line and the seventh line in FIG. 8B) for determining whether the stored values of the A register and the X register are NULL characters are included in this period. For this reason, the data transfer processing by the program of FIG. 8B also deteriorates the efficiency of the data transfer processing for the time consumed by repeated execution of the comparison instruction, as in FIG. 8A.

  The microcomputer according to the present invention includes an execution control unit that decodes an instruction, an arithmetic unit that executes arithmetic processing based on an instruction decoding result of the execution control unit, a first data storage unit, and the arithmetic unit Detection for detecting whether or not the data stored in the first data storage unit is a predetermined identification code in response to execution of a data transfer instruction between the first data storage unit and the second data storage unit Circuit.

  With such a configuration, it is possible to detect an identification code included in the transfer data, for example, a NULL character indicating the end position of the character string data, along with the execution of the data transfer instruction. For this reason, in the conventional microcomputer 70, when executing the data transfer process of the undetermined block data, it is not necessary to execute the comparison instruction necessary for detecting the end code such as the NULL character. In other words, the microcomputer according to the present invention can reduce the number of execution instructions when executing the data transfer process of the undetermined block data, so that the data transfer process efficiency can be improved as compared with the related art.

  According to the present invention, it is possible to provide a microcomputer with improved data transfer processing efficiency of unconfirmed block data.

  Hereinafter, specific embodiments to which the present invention is applied will be described in detail with reference to the drawings. In the drawings, the same elements are denoted by the same reference numerals, and redundant description will be omitted as necessary for the sake of clarity.

Embodiment 1 of the Invention
The microcomputer 10 according to the present embodiment is a microcomputer configured to be able to efficiently perform data transfer processing on unconfirmed character string data stored in the data memory 72. The configuration of the microcomputer 10 is shown in FIG.

  In FIG. 1, an end code determination circuit 110 is a circuit that detects a match between input data and an end code indicating an end position of block data. In the present embodiment, the end code determination circuit 110 detects a match with a NULL character indicating the end position of the character string data. Specifically, the end code determination circuit 110 outputs “1” when the input data matches the NULL character, and outputs “0” when the input data does not match the NULL character. If the block data that is the target of the data transfer process is not character string data, the end code determination circuit 110 may detect a match with the end code corresponding to the block data to be transferred.

  The data stored in the A register is input to the end code determination circuit 110. This is because, as will be described later, a register for storing 1-byte data acquired from the data memory 72 when executing data transfer processing of unconfirmed character string data is fixed to the A register. When the data acquired from the data memory 72 is stored in another general-purpose register different from the A register, this register may be used as the input source register of the end code determination circuit 110. Further, an input source register for the end code determination circuit 110 may be selectable. In this case, the execution control unit 101 that has decoded the data transfer instruction from the data memory 72 to the general-purpose register selects the general-purpose register indicated by the operand of the data transfer instruction as the input source register of the end code determination circuit 110. You may comprise.

  The selector 111 is a 2-input 1-output selector circuit. Selection of the input port of the selector 111 is performed according to a control signal output from the execution control unit 101. Specifically, when the execution control unit 101 decodes the MOVS instruction, the input terminal on the end code determination circuit 110 side is selected, and when the execution control unit 101 decodes an instruction other than the MOVS instruction, the other input terminal is selected. Is selected. Here, the MOVS instruction is a transfer instruction newly defined for performing data transfer processing of data including a predetermined identification code.

  Similar to the above-described conventional execution control unit 701, the execution control unit 101 decodes the instruction fetched from the instruction memory 71, and according to the information obtained by the instruction decoding, the program counter 702, the general-purpose register file 703, and the ALU 704 The data and / or the control signal are output to the selector 707 and the selector 709. In addition to this, the execution control unit 101 outputs a control signal to the selector 111 according to the result of instruction decoding.

  The other constituent elements shown in FIG. 1 are the same as those of the conventional microcomputer 70, and therefore, the same reference numerals are given to these constituent elements, and detailed description thereof will be omitted.

  Next, the operation of the selectors 707 and 111 according to the instruction decoding result in the execution control unit 101 will be described with reference to FIG. FIG. 2A shows a selection state of the selectors 707 and 111 when an arithmetic operation instruction such as an ADD instruction and an instruction other than the MOVS instruction are decoded. At this time, the value held in the Z flag 706 is repeatedly input to the Z flag 706 so that the stored value of the Z flag 706 is maintained.

  FIG. 2B shows a selection state of the selectors 707 and 111 when an arithmetic instruction such as an addition instruction (ADD instruction) is decoded. At this time, the selectors 707 and 111 operate so that the determination result of the zero determination circuit 705 is input to the Z flag 706.

  FIG. 2C shows a selection state of the selectors 707 and 111 when the MOVS instruction is decoded. At this time, the selectors 707 and 111 operate so that the determination result of the end code determination circuit 110 is input to the Z flag 706. As a result, since the determination result of the end code determination circuit 110 is held in the Z flag 706, the value of the Z flag 706 indicates whether or not the data read from the data memory 72 and stored in the A register is a NULL character. Can be determined.

  FIG. 3 shows a description example of a program when the microcomputer 10 executes data transfer processing of unconfirmed character string data. The program in FIG. 3 describes the data transfer process by a loop process that repeats the data transfer in units of 1 byte, as in FIG. The first line in FIG. 3 is a mere comment line, similar to the first line in FIG. The MOV instruction on the second line in FIG. 3 is a data transfer instruction, and reads 1-byte data from the storage area of the data memory 72 specified by the 16-bit address stored in the DE register and stores it in the A register. This instruction is the same as the MOV instruction in the second row in FIG.

  The third line in FIG. 3 is a MOVS command newly defined to perform data transfer of unconfirmed character string data. The first operand of the MOVS instruction indicates the data transfer destination, and the second operand indicates the data transfer source. The transfer instruction represented by the mnemonic “MOVS [HL], A” transfers the data stored in the A register to the storage area of the data memory 72 specified by the 16-bit address stored in the HL register. Shows the processing to be performed.

  Further, as described with reference to FIG. 2, when the MOVS instruction in the third row in FIG. 3 is executed, the determination result by the end code determination circuit 110 is input to the Z flag 706. That is, when the transfer source data stored in the A register is a NULL character (0x00), “1” is set to the Z flag 706, and when the transfer source data is not a NULL character, “0” is set to the Z flag 706. Therefore, in contrast to the program of FIG. 8A, the microcomputer 10 performs processing equivalent to the processing executed by the MOV instruction in the third row and the CMP0 instruction in the fourth row in FIG. It can be executed only by the MOVS instruction on the third line.

  The INCW instructions on the 4th and 5th lines in FIG. 3 are the same as the INCW instructions on the 5th and 6th lines in FIG. 8A, and the DE that stores the data transfer source address by these instructions. The HL register for storing the register and the data transfer destination address is incremented.

  Finally, the BNZ instruction on the sixth line in FIG. 3 is the same as the BNZ instruction on the seventh line in FIG. 8A, and branches to the first line when the Z flag 706 is set to “0”. Is a conditional branch instruction.

  As described above, the microcomputer 10 according to the present embodiment includes the end code determination circuit 110 that detects a match between the data transferred from the data memory 72 to the general-purpose register file 703 and a NULL character. Furthermore, when executing a predetermined transfer instruction for instructing data transfer from the general-purpose register file 703 to the data memory 72, specifically, a MOVS instruction, the termination code determination circuit 110 also detects a NULL character. The detection result of the end code determination circuit 110 is held in a predetermined flag register, specifically the Z flag 706. With such a configuration, it is not necessary to execute a comparison instruction that is necessary for detecting a NULL character in the conventional microcomputer 70. That is, since the microcomputer 10 can reduce the number of execution instructions when executing the data transfer process of the undetermined character string data, the processing efficiency of the data transfer process can be improved as compared with the related art.

Embodiment 2 of the Invention
The microcomputer 20 according to the present embodiment has improved the microcomputer 10 described above so as to have a configuration suitable for executing data transfer between the data memory 72 and the general-purpose register file 703 in units of 2 bytes. Is. FIG. 4 shows the configuration of the microcomputer 20 according to this embodiment.

  In FIG. 4, end code determination circuits 210 and 211 are the same circuits as the end code determination circuit 110 described above. That is, the end code determination circuits 210 and 211 are circuits that detect a match between the input data and the end code indicating the end position of the block data. Specifically, the end code determination circuits 210 and 211 output “1” when the input data matches the NULL character, and outputs “0” when the input data does not match the NULL character.

  The data stored in the X register is input to the end code determination circuit 210. On the other hand, the data stored in the A register is input to the end code determination circuit 211. This is because, as will be described later, the registers for storing the 2-byte data acquired from the data memory 72 when executing the data transfer process of the character string data are fixed to the A register and the X register. Note that the input source of the end code determination circuits 210 and 211 can be changed as appropriate, as described for the end code determination circuit 110 in the first embodiment of the invention.

  The OR circuit 212 receives the output signals of the end code determination circuits 210 and 211 and outputs the result of these OR determinations (logical sum operation). That is, when at least one of the data stored in the A register and the X register is a NULL character, when the output of at least one of the end code determination circuits 210 and 211 is “1”, the output of the OR circuit 212 is “1”. become.

  Each of the selector 213 and the selector 214 is a 2-input 1-output selector circuit. Selection of input ports of the selectors 213 and 214 is performed according to a control signal output from the execution control unit 201. Specifically, when the execution control unit 201 decodes the MOVS instruction, the selector 213 selects the input terminal on the end code determination circuit 210 side, and the selector 214 selects the input terminal on the OR circuit 212 side. On the other hand, when the execution control unit 201 decodes an instruction other than the MOVS instruction, the selectors 213 and 214 select the other input terminal.

  Similar to the above-described conventional execution control unit 701, the execution control unit 201 decodes an instruction fetched from the instruction memory 71, and according to information obtained by instruction decoding, a program counter 702, a general-purpose register file 703, and an ALU 704. The data and / or the control signal are output to the selector 707 and the selector 709. In addition to this, the execution control unit 201 outputs a control signal to the selectors 213 and 214 in accordance with the result of instruction decoding.

  FIG. 5 is a diagram illustrating operations of the selectors 707, 709, 213, and 214 when the execution control unit 201 decodes the MOVS instruction. That is, the four selectors 707, 708, 213, and 214 operate so that the output of the end code determination circuit 210 is input to the Z flag 706 and the output of the OR circuit 212 is input to the CY flag 708. Thus, it can be determined from the value of the CY flag 708 that at least one of the 2-byte data read from the data memory 72 and stored in the A register and the X register is a NULL character. Further, it can be determined from the value of the Z flag 706 that the data read from the data memory 72 and stored in the X register is a NULL character.

  FIG. 6 shows an example of a program in the case where the microcomputer 20 executes the data transfer process for the undetermined character string data. The program shown in FIG. 6 is described to be compared with the program shown in FIG. 8B, and the data transfer process is described by a loop process that repeats data transfer in units of 4 bytes. Data transfer to the general-purpose register file 703 is described using a 2-byte data transfer instruction (MOVW instruction).

  The first line in FIG. 6 is just a comment line, similar to the first line in FIG. The MOVW instruction on the second line in FIG. 6 is the same as the MOVW instruction on the second line in FIG. That is, it shows a transfer instruction for reading 2-byte data from the storage area of the data memory 72 specified by the 16-bit address obtained by adding the offset value “0” to the stored value of the DE register and storing it in the AX register.

  The MOVS instruction on the third line in FIG. 6 transfers the data stored in the X register to the storage area of the data memory 72 specified by the 16-bit address obtained by adding the offset value “0” to the stored value of the HL register. The process to transfer is shown. Further, when the MOVS instruction on the third line in FIG. 6 is executed, the determination result of the end code determination circuit 210 is input to the Z flag 706 and the output of the OR circuit 212 is output as described with reference to FIG. This is input to the CY flag 708.

  In the program of FIG. 8B, the instruction group corresponding to the MOVS instruction on the third line in FIG. 6 is the MOV instruction on the third line, the CMP0 instruction on the fourth line, and the CMP0 instruction on the seventh line. That is, the microcomputer 20 can execute processing corresponding to the conventional three instructions with one instruction by the MOVS instruction in the third row of FIG.

  The BC instruction on the fourth line in FIG. 6 is a conditional branch instruction that branches to the 19th line when the value of the CY flag 708 is “1”. That is, the BC instruction is an instruction for ending the loop process when it is determined that at least one of the data stored in the A register and the X register is a NULL character. This BC instruction corresponds to two BZ instructions on the fifth and eighth lines in FIG. In this embodiment, since the OR determination result for the 2-byte data stored in the A register and the X register is set in the CY flag 708, the end of the loop can be determined only by one conditional branch instruction (BC instruction). .

  The MOV instruction on the fifth line in FIG. 6 transfers the data stored in the A register to the storage area of the data memory 72 specified by the 16-bit address obtained by adding the offset value “1” to the stored value of the HL register. The process to transfer is shown. This is the same as the MOV instruction on the sixth line in FIG.

  The instructions from the sixth line to the ninth line in FIG. 6 are repetitions of the instructions from the second line to the fifth line in FIG. The 10th to 15th lines in FIG. 6 are instructions for incrementing the DE register storing the data transfer source address and the HL register storing the data transfer destination address. These instruction groups are the same as the instructions on the 16th to 21st lines in FIG. Further, the unconditional branch instruction (BR instruction) on the 16th line in FIG. 6 is the same as the instruction on the 22nd line in FIG. 8B.

  The 17th to 22nd lines in FIG. 6 are instruction groups for executing post-processing after exiting the loop processing from the 2nd to 16th lines. The 17th line in FIG. 6 is a comment line indicating a branch destination when the loop process is terminated. The 18th line in FIG. 6 is an instruction for incrementing the BC register used as a counter for calculating the offset value. The 19th line in FIG. 6 is a comment line indicating a branch destination at the end of the loop processing. The ROLWC instruction on the 20th line in FIG. 6 includes the contents of the register specified by the first operand (that is, the BC register) including the CY flag 708, and moves leftward the number of times specified by the second operand (that is, once). The command to rotate. Note that when the ROLWC instruction on the 20th line is executed, “1” is set in the CY flag 708. Therefore, by executing the ROLWC instruction, the contents of the BC register are shifted leftward, and “1” is set in the LSB (Least Significant Bit) of the C register. That is, if the original BC register value is n in decimal notation, the value of the BC register is updated to 2n + 1 by the execution of the ROLWC instruction on the 20th line.

  In the SKZ instruction on the 21st line and the MOV instruction on the 22nd line in FIG. 6, after the loop processing from the 2nd line to the 16th line is finished, the stored value of the A register is the end of the unconfirmed character string data, that is, NULL. If it is a character, it is an instruction for transferring it to the data memory 72. Specifically, the SKZ instruction on the 21st line is an instruction to skip the subsequent one instruction when the value of the Z flag 706 is “1”. On the other hand, the value of the Z flag 706 being “0” means that the data stored in the A register is a NULL character indicating the end of the undetermined character string data. Therefore, when the value of the Z flag 706 is “0”, the value of the A register is transferred to the data memory 72 by the MOV instruction on the 22nd line.

  The microcomputer 20 according to the present embodiment does not need to execute a comparison instruction that is necessary for detecting a NULL character in the conventional microcomputer 70. That is, since the microcomputer 20 can reduce the number of execution instructions when executing the data transfer processing of the undetermined character string data, the processing efficiency of the data transfer processing can be improved as compared with the conventional case.

  Further, the microcomputer 20 performs data transfer in units of 2 bytes between the data memory 72 and the general-purpose register file 703. If data transfer is performed in units of 2 bytes larger than the 1-byte unit that is the constituent unit of character data, there is a possibility that the character string data will end in the middle of the transfer data unit. For this reason, it is necessary to determine which of the data read from the data memory 72 in units of 2 bytes is a NULL character.

  In order to make this determination, the microcomputer 20 is configured so that a NULL character position can be identified by a plurality of flags. Specifically, the determination result whether or not at least one of the data read to the A register and the X register is a NULL character is set in the CY flag 708, and the data stored in the X register is set to a NULL character. Is set in the Z flag 706. That is, one of the two flags (CY flag 708) is set according to the OR determination result for the 2-byte data.

  With such a configuration, the data transfer is performed by one conditional branch instruction for the CY flag 708 that is set according to the OR determination for the 2-byte data, such as the BC instructions in the fourth and eighth lines in FIG. Therefore, it is possible to determine the end of the loop processing. That is, two conditional branch instructions for the Z flag 706 and the CY flag 708 are not required when determining the end of the loop processing. Therefore, it is possible to further improve the efficiency of the data transfer process of the undetermined character string data.

  In this embodiment, two 1-bit flags are used to support data transfer in units of 2 bytes. However, it is easy to extend this to arbitrary N bytes. Specifically, one flag that is set when any one byte of N-byte transfer data is an end code (NULL character), and which position of the N-byte transfer data is an end code (NULL character) N-1 flags indicating whether or not, a total of N 1-bit flags may be provided. Thus, by setting one of the 1-bit flags based on the OR determination result for N-byte data, the end of the loop processing for data transfer can be determined only by the value of one flag.

Other embodiments.
In the first and second embodiments of the invention, a flag register that holds a detection result of a NULL character, that is, an end code, is shared with the existing Z flag 706 and CY flag 708. However, an independent flag register may be provided without being shared with these. Further, the registers of the general-purpose register file 703 may be assigned to these flag registers. However, if the existing Z flag 706 and CY flag 708 are used, an instruction group prepared for an existing instruction set such as the BZ instruction and the BC instruction described above can be used. For this reason, there is an advantage that the development burden when the present invention is applied to an existing microcomputer can be reduced.

  In the program examples described in the first and second embodiments of the present invention, the detection results of the end code detection circuits 110, 210, and 211 in accordance with the execution of the data transfer command from the general-purpose register file 703 to the data memory 72 It has been described that the data is output to the CY flag 708. However, in conjunction with the execution of the data transfer instruction from the data memory 72 to the general-purpose register file 703 prior to this transfer instruction, the detection results of the end code detection circuits 110, 210 and 211 are stored in the Z flag 706 or the CY flag 708. It may be output.

  In the first and second embodiments of the present invention, data transfer processing of unconfirmed character string data is targeted, but the present invention can be applied to transfer of arbitrary unconfirmed block data. In this case, the end code determination circuits 110, 210, and 211 may detect the end code corresponding to the undetermined block data to be subjected to data transfer processing.

  In the first and second embodiments, the configuration in which the data memory 72 exists outside the microcomputers 10 and 20 has been described. However, for example, the data memory 72 may be present inside the microcomputers 10 and 20 such as a microcomputer integrated on one chip including the data memory 72. That is, the present invention is not limited to the specific implementation shown in Embodiments 1 and 2 of the invention, and can be applied to microcomputers of various implementation forms.

  In the first and second embodiments of the invention, the data transfer process using the data memory 72 as the transfer source and transfer destination of the indeterminate block data has been described. However, the instruction memory 71 may be the transfer source or transfer destination of the indeterminate block data, or both the transfer source and the transfer destination. For example, the present invention can be applied to data transfer processing in which data stored as table data in the instruction memory 71 is loaded into the general-purpose register file 703 and transferred to another memory (for example, the data memory 72). .

  Furthermore, the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the gist of the present invention described above.

It is a block diagram of the microcomputer concerning Embodiment 1 of invention. It is a figure for demonstrating operation | movement of the microcomputer concerning Embodiment 1 of invention. It is an example of a program description for making the microcomputer concerning Embodiment 1 perform a data transfer process. It is a block diagram of the microcomputer concerning Embodiment 2 of invention. It is a figure for demonstrating operation | movement of the microcomputer concerning Embodiment 2 of invention. It is an example of a program description for making the microcomputer concerning Embodiment 2 perform a data transfer process. It is a block diagram of the conventional microcomputer. It is an example of a program description for causing a conventional microcomputer to perform data transfer processing.

Explanation of symbols

10, 20 Microcomputer 101, 201 Execution control unit 110, 210, 211 End code determination circuit 111, 213, 214 Selector 212 OR circuit 71 Instruction memory 72 Data memory 73 Address bus 74 Data bus 702 Program counter (PC)
703 General-purpose register file 704 Arithmetic logic unit (ALU)
705 Zero determination circuit 706 Zero flag (Z flag)
707, 709 Selector 708 Carry flag (CY flag)
R0 to R15 general purpose registers

Claims (9)

An execution control unit for decoding instructions;
An arithmetic unit that executes arithmetic processing based on an instruction decoding result of the execution control unit;
A first data storage;
Whether the data stored in the first data storage unit is a predetermined identification code in response to the execution of a data transfer instruction between the first data storage unit and the second data storage unit by the arithmetic unit A detection circuit for detecting
A microcomputer comprising:   The detection circuit is configured to execute a command for outputting data from the first data storage unit to the second data storage unit, and to store data stored in the first data storage unit with a predetermined identification code. The microcomputer according to claim 1 which detects whether or not there is. A zero flag for storing that the calculation result by the calculation unit is zero;
A carry flag for storing occurrence of carry or borrow in the calculation result by the calculation unit;
The microcomputer according to claim 1, wherein a detection result of the detection circuit is stored in at least one of the zero flag and the carry flag.   The detection circuit, when data longer than the data length of the identification code is batch transferred to the first data storage unit, a determination result indicating that at least the identification code is included in the batch transferred data; 2. The microcomputer according to claim 1, wherein the microcomputer outputs a determination result for specifying a position of the identification code in the collectively transferred data.   5. The microcomputer according to claim 1, wherein the identification code is a data string indicating an end position of block data whose data length to be transferred is not predetermined.   The first data storage unit is a general-purpose register used as a storage location for input data to the calculation unit and output data of the calculation unit, and the second data storage unit is a data memory. Microcomputer. A microcomputer that performs transfer processing of block data whose data length to be transferred is not predetermined,
A first data storage;
A detection circuit for detecting whether data input to the first data storage unit is an end code indicating an end position of the block data;
A microcomputer comprising:   8. The detection circuit according to claim 7, wherein the detection circuit detects the end code in response to execution of a transfer instruction for inputting data to the first data storage unit or an instruction for outputting data from the first data storage unit. The microcomputer as described.   The detection circuit includes a determination result indicating that at least the end code is included in the batch transferred data when data longer than the data length of the end code is batch transferred to the first data storage unit. 8. The microcomputer according to claim 7, wherein the microcomputer outputs a determination result for specifying a position of the end code in the collectively transferred data.

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