JP3658101B2 - Data processing device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a data processing apparatus for executing an operation of a plurality of instruction codes, and more specifically to an instruction code arrangement technique in a processor.
[0002]
[Prior art]
Usually, in a processor, an instruction is stored as an instruction code in a memory connected to the processor via a data bus. In this case, the format of the instruction code stored in the memory includes (1) “fixed length format” in which the length of the instruction code is always set regardless of the type of instruction, and (2) There is an “arbitrary length instruction format” in which the length of the instruction code is set to differ depending on the type of instruction.
[0003]
The instruction code includes an operation code part that designates the function of the instruction, such as operation, transfer, and branch, and an operand code part that designates execution target data (operand) of the instruction. The designation of the operand is performed by designating whether the operand is stored in the register or in the external memory in the addressing mode designating part in the instruction code. If the operand is in the memory, address information is further added to the instruction code.
[0004]
The instruction formats of the fixed length format and the arbitrary length format are schematically shown in FIGS. 18 and 19, respectively. In both figures, instruction format 100 has no operand, instruction format 101 has an operand, instruction format 102 has an arbitrary length format without an operand, and instruction format 103 has an arbitrary length format with an operand. Respectively.
[0005]
[Problems to be solved by the invention]
(1) When instruction code is fixed length instruction format
In this case, there is an advantage that the instruction code can be easily decoded. However, this instruction format has a restriction that an operation code, an addressing mode designation part, and additional information such as address information must be described within a predetermined fixed instruction length. Therefore, in order to describe more additional information, it is necessary to set a large instruction length. As a result, in the fixed-length instruction format in which the instruction length is increased, there is a problem that redundant portions are increased in the instruction bit pattern and the code size is increased. On the other hand, if the instruction length is set small in order to reduce the code size, there arises a problem that the restriction on the instruction function becomes large.
[0006]
(2) When instruction code is in arbitrary length instruction format
In this case, since an instruction format having two or more arbitrary instruction lengths is used, there is an advantage that the instruction function can be expanded according to each instruction. In addition, since the instruction length of an instruction having no operand can be set short, there is an advantage that the code size can be reduced as compared with the case of the fixed-length instruction format.
[0007]
On the other hand, the data read from the memory is extracted as each instruction code, and further, the operation of decoding each instruction code itself is complicated, so that the instruction decoding method has to be complicated. For this reason, the H / W (hardware) for extracting the instruction code from the contents of the memory and sending it to the instruction decoder increases. For example, as shown in FIG. 20, when the 16/32 bit length instruction format 105, 104 is introduced as an arbitrary length instruction format, as shown in FIG. 21, between the instruction fetch unit and the instruction decoder, the instruction code Four routes need to be prepared for transfer. For this purpose, the instruction decoder must be provided with a complicated shift function so that a valid instruction code can be shifted and decoding can be performed under an appropriate instruction code arrangement.
[0008]
As described above, the fixed-length instruction format (1) and the arbitrary-length instruction format (2) have advantages and disadvantages. Therefore, it is desired to realize a processor having the advantages (1) and (2).
[0009]
The present invention has been made to realize the above-mentioned concerns. Specifically, (i) the code size is reduced as compared with the fixed-length instruction format, and (ii) the conventional arbitrary-length instruction format. The main object of the present invention is to realize a processor and an input device for a processor having an instruction format capable of increasing the speed by reducing the amount of H / W of the processor.
[0010]
Another object of the present invention is to realize a processor having functions of interrupts (external interrupts, PC break interrupts) generated during instruction execution and software interrupts.
[0011]
Another object of the present invention is to embody a configuration of a processor for decoding such an instruction code.
[0012]
[Means for Solving the Problems]
A data processing apparatus according to a first aspect of the present invention provides two types of instruction codes comprising only a first instruction data signal for giving an N (N is an integer of 1 or more) bit length instruction and a second instruction data signal for giving a 2N bit length instruction. The first and second instruction codes are: (1) storing the two first instruction data signals within a 2N-bit word boundary, and (2) the second instruction code. Instruction code input means arranged under the rule of storing each of two instruction data signals within a boundary of a 2N-bit word, and instruction fetch means for fetching an instruction code arranged in the instruction code input means And be prepared Each of the first and second instruction data signals includes instruction length identifier data for giving control information of the instruction execution order at the predetermined bit position. .
[0018]
DETAILED DESCRIPTION OF THE INVENTION
(Embodiment 1)
Here, an example where N = 16 will be described with reference to the drawings.
[0019]
FIG. 1 is a block diagram showing a configuration of a data processing apparatus that executes a plurality of operations according to the present invention. As shown in FIG. 1, the apparatus is configured with a processor 10 as a core.
[0020]
The processor 10 includes an arithmetic unit 1, a register 2, a program counter unit (hereinafter referred to as a PC unit) 3, an address generator 4, an instruction queue unit 5, an instruction fetch unit 6, an instruction decoding unit 7, and a control unit 8. It is made up of. Among these, the control unit 8 controls the operations of the units 1 to 7 in the processor 10 in accordance with the decoding result output from the instruction decoding unit 7. For simplification of illustration, illustration of each control signal output from the control unit 8 is omitted in FIG. The arithmetic unit 1 includes an ALU (arithmetic logic unit), a shifter, a load-store unit, and a multiplier (Mul.). The register 2 is a general-purpose register, has 16 signal lines with a 32-bit width, and holds operation result data and address data. Details of other components will be described later.
[0021]
The instruction queue unit 5 and the instruction fetch unit 6 are collectively referred to as “instruction fetch function unit”.
[0022]
Further, the processor 10, the external peripheral circuit 11, the memory 12, and the data selector 14 are connected by a data bus 15 and a bus interface unit 13. The data bus 15 corresponds to “input means” for inputting an instruction code data signal for giving an instruction code to the processor 10.
[0023]
I. Instruction code layout (instruction set)
Next, the “instruction code arrangement method” which forms the basis of the present invention will be described.
[0024]
As described above, the (1) fixed-length instruction format and the (2) arbitrary-length instruction format have merits and demerits, respectively. In particular, in the arbitrary length instruction format (2), when using two types of instruction codes, a 16-bit instruction code and a 32-bit instruction code, between the instruction fetch unit (or instruction queue unit) and the instruction decode unit Four transfer paths are required. Of these, the cause of the serious problem of hardware complexity is the arrangement of instruction codes that cause 32 (2N) bit length instructions to cross the 32 (2N) bit boundary. It seems to be forgiving. This point is schematically shown in FIG.
[0025]
Now, the instruction fetch units are arranged in the order shown in the upper part of the figure from the external memory. 3 It is assumed that one instruction code 106 to 109 has been fetched, and among these, the 32-bit instruction codes 107 and 108 are effective for data processing. In such a case, it is necessary to decode the valid instruction codes 107 and 108 in an arrangement as shown on the lower side of the figure. Therefore, it is necessary to realize two intersecting paths 110 and 111 as shown in FIG. The arrangement of the instruction code serving as such a path is referred to herein as “an arrangement in which 2N-bit instructions cross 2N-bit boundaries”. For this reason, the hardware on the instruction decoder side must be complicated. If attention is given to such factors, it is necessary to prohibit the placement of such instruction codes.
[0026]
Therefore, according to the present invention, (i) a plurality of instructions having only two types of instruction lengths, that is, an instruction (first instruction data signal) of N (N ≧ 1) bit length and an instruction of 2N bit length (second instruction data signal). (Ii) Instruction code arrangement method, that is, within a “word” given with a 2N-bit length (this is referred to as a 2N-bit word boundary) The method of arranging each instruction is limited to the following two types. That is,
(1) Two N-bit instructions are stored within a 2N-bit word boundary.
[0027]
(2) Store a single 2N bit long instruction within a 2N bit word boundary.
[0028]
In this embodiment, since the case of N = 16 is handled, there are only two types of instructions of 16-bit length instructions and 32-bit length instructions (instructions of the maximum bit length), and the instruction code arrangement method is as shown in FIG. It becomes.
[0029]
By providing such an arrangement restriction, instruction code arrangement in which a 32-bit instruction crosses a 32-bit boundary is completely prohibited. As a result, the instruction fetch unit 6 and the instruction decode unit in FIG. As shown in FIG. 4, the number of transfer routes to 7 is reduced to three types. These three types of transfer paths can be understood from the following schematic explanatory diagram 5.
[0030]
As shown in the figure, in the state held in the instruction queue unit 5, there can be three types of instruction code arrays. Among them, what is shown in the upper and middle stages of the figure is the case where only the preceding 16-bit instruction code A1 and the succeeding 16-bit instruction code B2 are valid. Arranged under the restrictions of 1). Among these, in the case of the upper stage in the figure, the instruction code A1 is transferred to the decoder via the path RT1 shown in FIG. In the case of the middle stage of FIG. 5, the instruction code B2 is transferred to the decoder via the crossing path RT3 shown in FIG. On the other hand, the 32-bit instruction code C1 shown in the lower part of FIG. 5 is arranged under the restriction based on the arrangement method (2), and is transferred to the decoder via the paths RT1 and RT2 shown in FIG. Is done. Therefore, only three types of routes RT1 to RT3 are required for decoding.
[0031]
As described above, since the arrangement of the instruction code is subject to the restrictions (1) and (2), the transfer path can be reduced by one type compared to the conventional case. An instruction code data signal for giving an instruction code arranged under the restrictions (1) and (2) is realized as an input data signal on the data bus 15 in FIG. . For this purpose, the instruction code data is written in the memory 12 by program control based on the constraint rules (1) and (2). Accordingly, the “memory 12” that stores the instruction code data signal written in the arrangement based on the restriction rules (1) and (2), and the instruction code data signal read from the memory 12 in accordance with the arrangement order are processed by the processor. The “data bus 15” that is a means for inputting into the processor 10 is generically referred to as a “processor instruction code input device”.
[0032]
Of the instruction code data signals, those that give a 16-bit (generally N-bit) length instruction code arranged based on the restriction (1) are referred to as “first instruction code data signal” and the restriction ( Those that give a 32-bit (generally 2N-bit) long instruction code arranged based on 2) are called “second instruction code data signals”, respectively.
[0033]
The format of the instruction code data signal in the instruction queue unit 5 of the processor 10 is shown in FIG. In the figure, symbols op1 and op2 represent operand codes, symbols R1 and R2 represent registers, symbol C represents a constant, and symbol cond represents branch condition designation.
[0034]
Instead of writing the instruction code data in the memory 12 under the restrictions (1) and (2), the instruction code data is written in the memory 12 regardless of the restrictions, and a new data bus 15 is written. A function unit for arranging the instruction code data signal read from the memory 12 under the restrictions (1) and (2) may be provided, and the output data of the function unit may be stored in the instruction queue unit 5. .
[0035]
II. Branch destination control
Further, in the processor 10, the branch destination address is specified or limited only to a 32-bit boundary. As described above, in addition to prohibiting the placement of the instruction code on the 32-bit boundary, the branch destination address is limited only to the 32-bit boundary, so that there are two types of transfer paths between the instruction fetch unit 6 and the instruction decoder. Reduced to
[0036]
This point can be easily understood by referring back to FIG. In other words, the restriction that the branch destination address can be specified only at the 32-bit boundary means that the instruction decoding unit 7 in FIG. 1 outputs the instruction arranged within the 32-bit long word boundary output from the instruction fetch unit 6. After receiving the code data signal, this means that the instruction code data signal starts to be decoded from its 32 bit (2N bit) boundary. Therefore, when two 16-bit instruction codes are arranged within a 32-bit word boundary, the preceding instruction A2 is decoded, and then the middle instruction code B2 in the figure has the preceding instruction code A2. What is necessary is just to decode after shifting to a bit position.
[0037]
Therefore, there are only two types of instruction code data signal transfer paths from the instruction queue unit 5 to the instruction decoding unit 7, as schematically shown in FIG. That is, the transfer path is
(A) Instruction queue part: upper 16 bits → instruction decode part: upper 16 bits
[0038]
(B) Instruction queue part: lower 16 bits → instruction decode part: lower 16 bits.
[0039]
The jump destination of a branch instruction is specified in the following format. This point will be described based on an instruction code table in the processor 10 shown in FIGS. In the above instruction code table, “dest” in “Format” indicates the register number of the result storage destination, and “src” is the object of calculation, and here means register R1 shown in FIG. The numerical value in the register R1 is the memory address value. “Pcdisp8” indicates that the immediate value is given by 8 bits.
[0040]
In the above instruction code table,
(A) For the JMP and JL instructions, the value of the register specified in the instruction code becomes the branch destination address. (However, the value “0” of the lower 2 bits of the register is ignored).
(B) The BRA, BL, BC, and BNC instructions specify 8-bit or 24-bit immediate values.
(C) The BEQ, BNE, BEQZ, BNEZ, BLTZ, BGEZ, BLEZ, and BGTZ instructions specify a 16-bit immediate value.
The branch destination addresses in (b) and (c) above are:
(PC value of branch instruction) + (value obtained by shifting the sign-extended immediate value to the left (to the most significant bit position) by 2 bits)
And However, when adding, the lower 2 bits of the PC value are “00”.
[0041]
As described above, since the branch destination is designated only on the 32-bit boundary, the lower 2 bits of the branch destination address are always “00”. Therefore, when the branch destination address is specified in the instruction code, it is not necessary to specify the lower 2 bits. As a result, the range that can branch directly from the instruction code is 2 ² Times, and thus 4 times. In the case of the present embodiment, as shown in the above instruction code table, since the address designation part in the instruction code is 24 bits at the maximum, it is possible to branch directly to the range of ± 32 MByte from the address of the instruction being executed. .
[0042]
III. Control instruction decoding order
Further, in the processor 10, information giving an instruction format identifier is provided in the instruction code as a predetermined number of bits, here 1 bit. The instruction decoding and execution order is controlled based on the value of the instruction format identifier. Here, the MSB (Most Significant Bit) of each instruction code corresponds to the instruction format identifier.
[0043]
The rule of control using the instruction format identifier is set as follows. That is, the MSB of a single 32-bit length instruction code is always set to 1. On the other hand, when the instruction code is composed of two 16-bit instruction codes, the MSB of the instruction code existing on the upper 16 bits side is always 0. Subsequent lower 16-bit instruction codes are processed differently depending on the MSB value.
[0044]
A method for controlling the execution order of instructions will be described with reference to FIG. In the figure, (1) When the MSB of “instruction B” is 0, “instruction A” and “instruction B” are executed successively.
[0045]
On the other hand, when (2) MSB of “instruction B” is 1, only “instruction A” is executed. Instruction B is not executed. That is, when the word alignment adjustment “NOP instruction” is inserted as the instruction B for word alignment adjustment based on the instruction code arrangement restriction of the 32-bit length instruction, the assembler automatically sets the instruction code corresponding to the “NOP instruction”. Thus, only the “instruction A” is executed. The normal invalid operation “NOP instruction” is given as “0111000000000000”, but for the above purpose of alignment, the “NOP instruction” was inserted into the lower 16-bit position within the 32-bit word boundary, There is no need to execute it directly. Therefore, in the processor 10, the “NOP instruction” is given as “1111000000000000000”, and as a result, the “NOP instruction” itself is not executed.
[0046]
By controlling the instruction execution order as described above, there is an advantage that there is no execution time penalty for the “NOP instruction” which is an invalid operation inserted to satisfy the code arrangement.
[0047]
V. Instruction decoding method and its control unit
Hereinafter, a specific example of the instruction decoding control method will be described with reference to FIG.
[0048]
(Configuration of instruction decode unit 7)
The instruction decode unit 7 includes an instruction decode input latch 7a, an instruction decoder 7c, a constant generator 7d, and a control logic 7b of the instruction decode unit 7. Among these, the control logic 7 b controls each part of the instruction decoding unit 7. The instruction decoder 7c receives a valid instruction code of the 32-bit bit pattern stored in the instruction decode input latch 7a as an input, and the instruction decoder 7c decodes the instruction code. The instruction code arrangement in the instruction decode input latch 7 a is the same as the instruction code arrangement on the memory 12. The decoding result is output to the control unit 8 of the processor 10, and the control unit 8 controls the arithmetic unit 1 and the entire processor 10 based on the decoding result.
[0049]
The detailed operation of each part is as follows.
[0050]
(Instruction fetch unit 6)
First, the instruction fetch unit 6 fetches an instruction code data signal from the memory 12 in units of 32 bits through the data bus 15 (FIG. 1), and stores them in the instruction queue unit 5. Further, the instruction fetch unit 6 sequentially reads out the instruction code data signal from the instruction queue unit 5 and transfers it to the instruction decoding unit 7 in accordance with a fifth control signal CB described later. As a result, the transferred instruction code data signal is stored in the 32-bit instruction decode input latch 7a.
[0051]
Execution of decoding of a signal giving a valid instruction code among the instruction code data signals stored in the instruction decode input latch 7a is controlled by the control logic 7b as follows based on the instruction format identifier described above. . This will be described in detail below.
[0052]
(Control logic 7b)
FIG. 13 shows the relationship between the first to third control signals CT1 to CT3 (also referred to as input signals) in FIG. 12 and the valid code arrangement in the instruction decode input latch 7a. The hatched portion in the figure indicates an instruction format identifier, and the satin portion indicates a valid code.
[0053]
As shown in FIG. 12, the control logic 7b outputs the first and second control signals CT1 and CT2 that give the instruction length identifier of the 32-bit pattern stored in the instruction decode input latch 7a, and the control logic 7b itself. The third control signal CT3 is input. That is, the instruction decode input latch 7a uses the value of the 0th bit and the value of the 16th bit of the 32-bit bit pattern held as an instruction format identifier as the first control signal CT1 and the second control signal CT2, respectively. Output to the control logic 7b. The third control signal CT3 is an output signal from the control logic 7b itself, which is the 0th bit in the 32-bit bit pattern stored in the latch 7a in response to the decode end signal ES output from the instruction decoder 7c. Whether the part from the 15th bit to the 15th bit is decoded (in this case “0”), or whether the part from the 16th bit to the 31st bit is currently decoded (in this case “1”) Represents.
[0054]
(Α) When the value of the first control signal CT1 is “1”, the instruction code data signal stored in the instruction decode input latch 7a gives a 32-bit instruction.
[0055]
(Β) When the first control signal CT1 is “0”, the instruction code data signal composed of two 16-bit instructions is stored in the instruction decode input latch 7a. At this time, if the second control signal CT2 is "0" and the third control signal CT3 is "0", a valid instruction code is on the upper 16 bits side. On the other hand, if the second control signal 2 is “0” and the third control signal CT3 is “1”, a valid instruction code is on the lower 16 bits side.
[0056]
(Γ) When the first control signal CT1 is “0” and the second control signal CT2 is “1”, only the upper 16-bit instruction code is a valid code, and the lower 16-bit instruction code is The above-described “NOP instruction” for word alignment adjustment is not executed.
[0057]
Based on the values of the input signals CT1 to CT3, the control logic 7b outputs the following three types of control signals CA, CB, and CT3 for decoding the next code. Among them, the fourth control signal CA is a control signal for shifting the lower 16-bit instruction code to the upper 16-bit position in the instruction decode input latch 7a, that is, a shifter control signal, and the fifth control signal CB is an instruction. This is a 32-bit boundary pointer of the address, and is a signal for instructing the instruction fetch unit 6 to start transfer of the instruction code to the instruction decode input latch 7a. As described above, the third control signal CT3 is a signal indicating whether the next valid code is in the upper 16-bit position or the lower 16-bit position in the 32-bit word boundary.
[0058]
Further, as shown in FIG. 12, the control logic 7b sets “1” as the sixth control signal CC when the address of the instruction code being decoded in the instruction decoder 7c is on a 32-bit word boundary. If it is not on the boundary, “0” is output to the PC bit 30 (PC 30) described later.
[0059]
When decoding a branch instruction that designates a branch destination address by an immediate value in the instruction code, that is, the above-mentioned (b) BRA instruction or (c) BEQ instruction, the latter 24 bits (8 bits) of the instruction decode input latch 7a The latch 7a outputs an immediate value to the constant generator 7d connected to the position (from the first to the 31st bit). The constant generator 7d outputs a value obtained by sign extending the immediate value to the bus S2.
[0060]
When a branch occurs during the execution of an instruction, the fourth control signal CA, the fifth control signal CB, and the sixth control of the instruction decoding unit 7 regardless of the values of the first to third control signals (inputs) CT1 to CT3. The signal CC and the third control signal CT3 are all initialized.
[0061]
The relationship between the control signal (input) and the control signal (output) is shown in FIG.
[0062]
As described above, in any case, in the instruction decode unit 7 (FIGS. 1 and 12), the instruction code to be decoded for the first time always starts from the head of the instruction decode input latch 7a. Therefore, the contents of instruction decode input latch 7a are transferred to instruction decoder 7c as they are. When the instruction code data signal is a single 32-bit instruction code, the transfer path is paths P2 and P3 shown in FIG. The transfer path for the upper 16-bit instruction code is path P2.
[0063]
Only when the instruction code arrangement in the instruction decode input latch 7a is sequential execution of a 16-bit instruction, the instruction code is output to the instruction decoder 7c for the second time. At this time, the following processing is performed before the second output to the instruction decoder 7c. Since the instruction code to be decoded, that is, the valid code is in the lower 16-bit position within the 32-bit word boundary, the contents of the instruction decode input latch 7a are to the left (toward the 0th bit of the 32-bit bit pattern). ) Shifted by 16 bits (path P1) and enter the input latch 7a. The result is the second output to the instruction decoder 7c (path P2).
[0064]
In this way, the route P1 is routed only when the valid code is in the lower 16-bit position of the instruction decode input latch 7a, so the amount of H / W can be reduced and the speed can be further increased. Is possible.
[0065]
VI. PC unit 3 increment operation
FIG. 15 is an enlarged block diagram of the PC unit 3 and the address generator 4 in FIG. The increment operation of the PC unit 3 will be described with reference to FIG.
[0066]
The address generator 4 includes a shifter 4a and an adder 4b, and calculates the address of the branch instruction according to the addressing mode.
[0067]
The PC unit 3 has a program counter (hereinafter referred to as PC) as a core, and further includes a comparator 3b, a (+1/0) unit 3e, a backup program counter (hereinafter referred to as BPC) 3f, a BPC 30 unit 3g, and a program counter. A break pointer (hereinafter referred to as PBP) is used. Among these, the PBP 3a and the BPC 3f are control registers.
[0068]
The above-mentioned program counter is a 32-bit counter and holds the address value of the instruction currently being executed. Since the instruction code arrangement method is limited as described above, the instruction of the processor 10 (FIG. 1) starts only from the even address value. Therefore, the value of the 31st bit of the program counter is fixed to “0” as illustrated in FIG. Therefore, since it is not necessary to realize the value of the 31st bit of the PC on the hardware, the PC gives the values from the 0th bit to the 29th bit as shown in FIG. 15 (0:29) 3c And the PC 30 unit 3d that gives the value of the 30th bit. Among these, the PC 30 unit 3d is a register that holds the value “0” or “1” of the sixth control signal CC.
[0069]
The BPC saves a PC value held by the PC 3c when an interrupt / trap described later occurs. Here, as illustrated in FIG. 23, since the value of the 31st bit of the BPC is always fixed to “0”, the BPC gives the values from the 0th bit to the 29th bit on the hardware. This is realized by (0:29) 3f and the BPC 30 giving the value of the 30th bit. Therefore, the processor 10 (FIG. 1) saves the value of the PC (0:29) 3c to the BPC (0:29) 3f when detecting the occurrence of an interrupt / trap described later. On the other hand, the PBP 3a is a 32-bit width control register for controlling a PC break interrupt, which will be described later, and the PBP 3a holds in advance an instruction execution address value that activates the interrupt, from the control unit 8 (FIG. 1). The address value is written using a write command signal on the output bus D1.
[0070]
The update of the PC (0:29) 3c is performed as shown below when an instruction other than a branch is executed in the processor 10 (FIG. 1). Here, four buses S1, S2, S3 and D1 are used, and the signal line D is connected to the PC 3c.
[0071]
When the fifth control signal CB (pointer indicating the address of the 32-bit word boundary) output from the control logic 7b of the instruction decoding unit 7 in FIG. 12 is updated, the value held by the PC (0:29) 3c is ( The value is increased by “+1” by the (+1/0) section 3e, and the increased value is placed on the signal line D. On the other hand, when the fifth control signal CB is not updated, the value of the PC (0:29) 3c is directly increased on the signal line D without being increased by the (+1/0) unit 3e.
[0072]
The value on the signal line D is written to the PC (0:29) 3c, whereby the PC value of the PC (0:29) 3c is rewritten to the value of the PC (0:29) 3c of the next instruction. Since the signal line D is connected to the bus S1, the updated value of the PC (0:29) 3c can be called on the bus S1.
[0073]
The value of the sixth control signal CC output from the control logic 7b (FIG. 1) in the instruction decoding unit 7 is written in the PC 30 unit 3d when the instruction is executed.
[0074]
On the other hand, if a branch occurs during instruction execution, the PC value of the next instruction is generated using the address generator 4, and the generated value is written to the PC (0:29) 3c via the bus S3. .
[0075]
Further, in the case of a branch instruction (the branch instructions (b) and (c) described above) in which jump address designation is performed with an immediate value, the constant generator 7d (FIG. 1) of the instruction decode unit 7 extracts the instruction code from the instruction code. The expanded immediate value is expanded to 32 bits, and the expanded immediate value is output to the address generator 4 via the bus S2. Then, the sign-extended immediate value is shifted by 2 bits to the left (to the most significant side) by the shifter 4a in the address generator 4. The updated value of PC (0:29) 3c is output from the signal line D to the address generator 4 via the bus S1. Here, the updated value of PC (0:29) 3c corresponds to the upper 30 bits of the PC of the branch instruction. The adder 4b
(Update value of PC (0:29) 3c) + (value obtained by shifting the sign-extended immediate value to the left by 2 bits)
Thus, the upper 30 bits of the branch destination address are obtained. The value of the upper 30 bits is written to the PC (0:29) 3c via the bus S3.
[0076]
In the case of a branch instruction in which the jump destination is specified by the value of register 2 (FIG. 1) (the above branch instruction (a)), the register 2 specified by the instruction code is held in the register via the bus S1. Value is received and the constant value is written to PC3c.
[0077]
When a branch occurs, the instruction decode unit 7 initializes the sixth control signal CC to “0”, so that “0” is written in the PC 30 unit 3d. Therefore, in the processor 10 (FIG. 1), as described above, the branch destination address is only a 32-bit word boundary.
[0078]
VII. Explanation of interrupt / trap operation
When a certain event occurs while the processor 10 (FIG. 1) is executing a normal program, it is necessary to interrupt the execution of the program and execute another program. Such events are roughly classified into interrupt and trap operations.
[0079]
(A) Interrupt (Interrupt)
Among the above events, an event generated by an external hardware signal (referred to as an interrupt request signal) or a PC break signal generated when a specific address is executed.
[0080]
(B) Trap
Among the above events, events issued by instructions.
[0081]
The processor 10 (FIG. 1) also has a function of realizing two types of (a) interrupts including an external interrupt (EI) and a PC break interrupt (PBI) and one type of trap (TRAP).
[0082]
The processing procedure when an interrupt / trap occurs will be described with reference to FIG.
[0083]
When the interrupt request signal or PC break signal becomes valid, the processor 10 interrupts only at a 32-bit word boundary, as will be described in detail later. See Accept. The trap instruction starts trap processing after execution of the instruction.
[0084]
As a result, the processor 10 (FIG. 1) interrupts execution of the program and performs interrupt or trap processing. At that time, as will be described later, the processor 10 detects an interrupt or trap event and saves the PC value of the PC 3c in FIG. 15 to the BPC 3f. Thereafter, the processing program corresponding to each interrupt or trap Branch to “Interrupt / Trap handler”.
[0085]
When the processing in the “interrupt / trap processing handler” is completed, a return instruction from the “interrupt / trap processing handler” is executed, and then the PC value of the PC 3c is restored, and the processor 10 returns from the interrupt / trap processing. To do.
[0086]
As described above, the interrupt / trap processing in the processor 10 includes a part for processing by hardware and a part for processing by a program. That is, in the processor 10, among the above processes,
(1) Saving the PC value that is the return destination to BPC3f,
(2) Branch to “interrupt / trap handler”
(3) Write BPC value to PC3c,
Is executed by the hardware part.
[0087]
The aforementioned external interrupt (EI) is generated by an external hardware signal (interrupt request signal). An interrupt request by an interrupt request signal is accepted only on a 32-bit word boundary (this mechanism depends on the configuration of a detection circuit described later). The value saved in the BPC 3f in FIG. 15 when an interrupt occurs is the PC value of the next instruction.
[0088]
On the other hand, a PC break interrupt (PBI) occurs when a specific address is executed. In the processor 10 (FIG. 1), the designated address is only a 32-bit word boundary. For each cycle, the comparator 3b of FIG. 15 compares the value held by the PBP 3a with the value of the PC 3c, and outputs a PC break signal 18 when the two values match. The PC break signal 18 is detected as an interrupt / trap detection signal via an interrupt / trap detection circuit described later, and the signal is output to the (+1/0) section 3e in FIG. As a result, an interrupt occurs in the processor 10 and the PC value is saved. As described above, writing to the PBP 3a is performed using the data bus D1. The value saved in the BPC 3f when an interrupt occurs is the PC value of the next instruction.
[0089]
A trap is an interrupt controlled by software, and is generated by execution of a trap instruction. In this case, information indicating whether the trap instruction is on the upper 16 bits side or the lower 16 bits side in the 32-bit word boundary is stored in the BPC bit 30, that is, the BPC 30 unit 3g. When the trap instruction is in the upper 16 bits, the value of the BPC 30 part 3g is “0”, and when the trap instruction is the lower 16 bits, the value of the BPC 30 part 3g is “1”. The value saved in the BPC when an interrupt occurs is (PC value of trap instruction +4).
[0090]
A circuit for detecting an interrupt / trap is shown in FIG. The detection circuit constitutes a part of the control unit 8 of FIG. 1, and includes an inverter 22, AND circuits 23 and 24, and an interrupt / trap detection circuit 16.
[0091]
The processor 10 accepts both the interrupt request by the external signal 19 and the interrupt request by the PC break signal 18 only at the 32-bit word boundary by the detection circuit. That is, since the level of the sixth control signal CC is “0” at the 32-bit word boundary, the word boundary detection signal 21 (its level is “1”) obtained by inverting the sixth control signal CC and the interrupt request signal 19 The output signal VE becomes valid ("1") only when the signals are simultaneously valid ("1"). Further, the output signal VF is valid only when the word boundary detection signal 21 and the PC break signal 18 are simultaneously valid (“1”). In this way, the above interrupt request is accepted only at a 32-bit word boundary, and after branching to the interrupt / trap processing handler and executing the processing, the interrupt / trap processing handler executes the return instruction by executing the return instruction. A return from the trap processing to the execution program is performed.
[0092]
On the other hand, in the trap instruction, when an interrupt by the trap instruction is instructed, the trap request signal 20 becomes valid (“1”).
[0093]
When any one of the trap request signal 20, the output signal VE, and the output signal VF becomes valid (“1”), the interrupt / trap detection circuit 16 outputs the interrupt / trap detection signal 17. When the interrupt / trap detection signal 17 is output, the process branches to an interrupt / trap processing handler, performs the processing, executes a return instruction, and returns from the processing to the execution program.
[0094]
As described above, when an interrupt / trap occurs, the value of PC3c (FIG. 15) is saved in BPC3f. When an interrupt occurs, the PC value of the next instruction is written into BPC3f.
[0095]
For example, when an interrupt occurs immediately after execution of a branch instruction, the PC value that gives the branch destination generated by the address generator 4 in FIG. 15 is BPC3f via the bus S3 under the control of the control unit 8. Is written to. On the other hand, when an interrupt occurs immediately after execution of an instruction other than a branch instruction, the (+1/0) unit 3e adds “+1” to the output value of the PC (0:29) 3c. , BPC (0:29) 3f.
[0096]
The value of the PC 30 part 3d is written in the BPC 30 part 3g. In the present processor 10 (FIG. 1), as described above, an interrupt is accepted only at a 32-bit word boundary. Therefore, the value saved in the BPC 30 unit 3g when an interrupt occurs is always “0”.
[0097]
When a trap occurs, the value of ((trap instruction PC) +4) is written into the BPC 3f. That is, a value obtained by adding “+1” to the output value of the PC (0:29) 3c by the (+1/0) unit 3e is written into the BPC (0:29) 3f, and the BPC 30 unit 3g includes the PC 30 unit 3d. The value of is written. That is, if the trap instruction that generated the trap is in the upper 16 bits of the 32-bit word boundary, “0” is in the BPC30 part 3f, and if it is in the lower 16 bits of the 32-bit word boundary, it is in the BPC30 part 3g. “1” is written respectively.
[0098]
As described above, the return from the interrupt / trap is performed by executing the return instruction. The return instruction receives the signal 25 output from the control unit 8 and branches to an address given by the signal output from the BPC 3f. However, in this processor 10, since the branch destination address is always set only at a 32-bit boundary, when the BPC 3f returns to the PC 3c, the lower 2 bits of the PC are always “00”.
[0099]
(Summary)
By adopting the above configuration, the following feature points can be obtained.
[0100]
The processor 10 executes an instruction code having two instruction lengths of N bit length and 2N bit length, thereby reducing the code size without being restricted by the instruction function as compared with the fixed length instruction format. The instruction decoding method can be simplified as compared with the conventional arbitrary length instruction format.
[0101]
In particular, a certain restriction is imposed on the instruction code arrangement to prohibit the instruction arrangement across the 2N-bit boundary, and the branch destination address is designated only on the 2N-bit word boundary. The data transfer path between the instruction decode units 7 can be significantly reduced. As a result, the H / W amount for instruction decoding can be reduced and the speed can be increased.
[0102]
In addition, in this processor 10, since the branch destination address is restricted to a 2N-bit boundary, the lower 2 bits of the branch destination address are always “00”. Therefore, it is not necessary to specify the lower 2 bits of the branch destination address in the instruction code. As a result, compared to specifying all bits of the address, 2 ² It is possible to branch directly from the address of the instruction being executed to a double, that is, four times as wide.
[0103]
The processor 10 having such a function can be further provided with a function capable of supporting various interrupts and trap processes.
[0104]
【The invention's effect】
Claim Described in 1 According to Ming, since both the first instruction data signal and the second instruction data signal are stored within the 2N bit word boundary by the instruction code input means, the data of the 2N bit length instruction crosses the 2N bit boundary. Arrangement of instruction codes that would otherwise be prohibited is prohibited. For this reason, there is an effect that the transfer path of the instruction code data signal from the instruction fetch unit to the instruction decode unit can be reduced from four types to three types.
[0106]
Further claims 1 According to the described invention, it is possible to control the decoding of each instruction and the execution order thereof based on the instruction length identifier. Depending on the proper installation of the instruction length identifier, it is possible to eliminate the execution of the instruction code data signal as an invalid operation, thereby eliminating the execution time penalty. When There is an advantage.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a data processing apparatus.
FIG. 2 is a diagram schematically showing an instruction code arrangement method;
FIG. 3 is a diagram schematically showing an instruction code arrangement method;
FIG. 4 is a diagram schematically illustrating a transfer path between an instruction fetch unit and an instruction decode unit.
FIG. 5 is a diagram showing an array of three types of instruction codes.
FIG. 6 is a diagram illustrating a format of an instruction code data signal in an instruction queue unit.
FIG. 7 is a diagram schematically illustrating a transfer path between an instruction queue unit and an instruction decoding unit.
FIG. 8 is a diagram showing a processor instruction code table;
FIG. 9 is a diagram showing a processor instruction code table;
FIG. 10 is a diagram showing a processor instruction code table;
FIG. 11 is a diagram illustrating a method for controlling the execution order of instruction codes.
FIG. 12 is a block diagram illustrating details of a configuration of an instruction decoding unit.
FIG. 13 is a diagram showing a relationship between first to third control signals and a valid code arrangement in an instruction decode input latch.
FIG. 14 is a diagram illustrating a relationship between first to third control signals and fourth to sixth control signals of control logic of the instruction decode unit;
FIG. 15 is a block diagram showing details of the configuration of a PC unit and an address generator.
FIG. 16 is a diagram showing a processing procedure when an interrupt / trap occurs.
FIG. 17 is a block diagram showing a circuit for detecting an interrupt / trap.
FIG. 18 is a diagram illustrating a conventional fixed-length instruction format.
FIG. 19 is a diagram showing a conventional arbitrary length instruction format.
FIG. 20 is a diagram showing a specific example of a conventional arbitrary length instruction format.
FIG. 21 is a diagram illustrating a transfer path between a conventional instruction fetch unit and an instruction decoder unit.
FIG. 22 is a diagram illustrating an aspect in which a PC is realized on hardware.
FIG. 23 is a diagram illustrating a mode in which BPC is realized on hardware.
[Explanation of symbols]
1 arithmetic unit, 2 register, 3 PC unit, 3a program counter / break pointer, 3b comparator, 3c program counter unit (bits 0 to 29), 3d program counter unit (bit 30), 3e (+1/0) unit, 3f Backup program counter (bits 0 to 29), 3g Backup program counter (bit 30), 4 Address generator, 5 Instruction queue section, 6 instruction fetch section, 7 Instruction decode section, 7a Instruction decode input latch, 7b control Logic, 7c instruction decoder, 7d constant generator, 8 control unit, 10 processor, 11 peripheral circuit, 12 memory, 13 bus interface unit, 14 data selector, 15 data bus, 16 interrupt / trap detection circuit, 17 interrupt / trap Detection signal, 18 PC break signal, 9 an interrupt request signal, 20 TRAP request signal, 21 word boundary detection signal, 22 an inverter, 23, 24 the AND circuit 25 output signal.

Claims (1)

A data processing apparatus that executes two types of instruction codes consisting of only a first instruction data signal that gives N (N is an integer of 1 or more) bit length instructions and a second instruction data signal that gives 2N bit length instructions,
The first and second instruction codes (1) store the two first instruction data signals within a 2N-bit word boundary, and (2) each of the second instruction data signals have a 2N-bit length. Instruction code input means arranged under the rule of storing within the boundaries of
E Bei an instruction fetch unit for fetching an instruction code placed in the instruction code input means,
Each of the first and second instruction data signals includes instruction length identifier data for giving control information of the instruction execution order at the predetermined bit position.
Data processing device.

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