JPH05313894A - Information processor - Google Patents

Abstract

PURPOSE:To execute instruction at a high speed by separating a branching destination instruction among the instruction executed by a pipeline system into an operation code and an operand to be stored along with the address of the branching destination. CONSTITUTION:In the information processor for executing an instruction set constituted of the instructions with the plural kinds of instruction lengths by the pipeline system, an instruction prefetch device 11 prefetches a variable length instruction and an instruction decoder 12 separates the instruction into the operation code and the operand to be temporarily stored in an instruction prefetch buffer 13. Then, the instruction decoder 16 of the pipeline system receives the operation code at every byte from the buffer 13 to be decoded. An instruction executing part 17 executes the instructions using the operand corresponding to the decoded instruction and separates the branching destination instruction among them into the operation code and the operand to be stored in a branch target cache 15 along with the branching destination address.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus, and more particularly to an information processing apparatus having a branch target cache for executing branch instructions at high speed.

[0002]

2. Description of the Related Art Conventionally, an information processing apparatus such as a computer stores instructions to be executed in a main memory constructed by using a dynamic random access memory, sequentially fetches and decodes the instructions to a central processing unit, and prepares operands. The process is performed in the order of executing and executing and storing the result. Generally, a pipeline method is adopted to increase the processing speed. When using the pipeline method, an instruction prefetch buffer is provided in front of the instruction decode stage in order to prevent the contention of access to the main memory between each pipeline stage and the disturbance of the flow of the pipeline. Store a few instructions that will be executed. However, in the pipeline method having the instruction prefetch buffer as described above, when an instruction that changes the flow of instructions such as a branch instruction, a procedure call, and a return is executed, the instruction group waiting for execution in the instruction prefetch buffer at that time is Not only is it wasted without being executed, but the pipeline is stopped until the instruction at the branch destination is fetched. In order to avoid this problem, a means for caching all the instructions is provided (see Japanese Patent Application Laid-Open No. 63-56731), and in the case of a RISC processor having a fixed length instruction set, "Am29000" is used. (32-
Bit. Streamlined. Instructi
on Processor) 32-bit RISC Microprocessor User's Manual (Japanese Version), Volume 1 (Japan AMD Co., Ltd., January 1989) ”, the branch destination instruction is branched together with the address when the branch instruction occurs. When the branch instruction is cached in the target cache and the branch instruction is executed next time, the branch target address is compared with the address cached in the branch target cache. It is devised so that processing can be continued without stopping the flow of the pipeline.

[0003]

However, in the architecture in which the instruction length is variable in order to minimize the area occupied by the program in the main memory, the instruction decoding stage takes a long time. In the pipeline method, the processing time of each stage is set to be equal,
The processing time is determined by the stage with the longest processing time. Therefore, if the processing time of the instruction decode stage is large as described above, the processing time of all the other stages is regulated to that. Therefore, the architecture in which the instruction length is variable in the pipeline method is applied. It was difficult. In order to solve this problem, it is conceivable to partially decode the instructions stored in the instruction prefetch buffer in advance. According to this, because it executes a variable length instruction set,
Since the instruction length is determined and the operands included in the instruction code are separated in advance, it is considered that the decode stage of the pipeline can be executed at high speed. However, in the case where a part of the instruction is decoded and stored in the buffer in advance as described above, the branch target cache described above cannot be effectively used.
In other words, even if the cache hits when a branch instruction occurs, it is necessary to determine the instruction length of the instruction in the branch target cache and to separate the operands included in the instruction code. To
There was a problem that the effect of the branch target cache was halved. Therefore, in the present invention, in view of the above circumstances, in an information processing apparatus that executes an instruction set including instructions of a plurality of types of instruction lengths by a pipeline method, it is possible to execute instructions at higher speed. The purpose is to In the present invention, an object of the present invention is to cache a predecoded instruction in a branch target cache in advance, and when the branch target cache caches a branch target instruction when a branch instruction occurs, an instruction from the branch target cache is stored. This is achieved by inputting the operation code and operand of each instruction in the buffer in a predecoded form, and reducing the pipeline overhead due to the branch instruction and the instruction fetch waiting time.

[0004]

In order to solve the above-mentioned problems, the information processing apparatus of the present invention comprises a prefetch means (1 in FIG. 1) for prefetching at least one variable length instruction.
1), a separating means (12) for separating a variable length instruction prefetched by the prefetching means into an operation code and an operand, and at least one instruction consisting of a set of an operation code and an operand separated by the separating means. And an instruction executing means (1) for executing the instruction stored in the instruction storing means by a pipeline method.
6, 17) and at least one branch destination instruction of the instructions executed by the instruction executing means is separated into an operation code and an operand and stored together with the branch destination address ( 15) and are provided.

According to a specific aspect of the present invention, the prefetch means can collectively prefetch a plurality of variable length instruction groups at a time.

Further, in a specific embodiment of the present invention, the separating means determines the instruction length of each instruction included in the instruction group prefetched by the prefetch means to identify the operation code and operand of each instruction, Has the function of separating.

In a specific embodiment of the present invention, the instruction storage means has a capacity of storing a predetermined plurality of instructions each consisting of a set of operation codes and operands separated by the separation means. -Memory can be used.

Further, in a specific aspect of the present invention, an associative memory having a branch destination head address as a key can be used as the branch destination instruction storage means.

Further, in a specific aspect of the present invention, the instruction executing means checks whether or not a branch destination instruction is stored in the branch destination instruction storage means when a branch instruction occurs, and the branch destination instruction is stored. Is stored, it has a function of transferring the branch destination instruction of the branch destination instruction storage means to the instruction storage means.

Further, in a specific embodiment of the present invention, the instruction storing means has a capacity for storing a predetermined plurality of instructions each consisting of a set of operation codes and operands separated by the separating means, and the branch destination. The instruction storage means has a storage capacity capable of storing a plurality of blocks in the same instruction storage capacity as the predetermined instruction storage capacity of the instruction storage means, and one branch instruction is associated with each block. It stores a branch destination instruction group, and is configured to transfer information from the branch destination instruction storage means to the instruction storage means at once in the block unit.

Further, in a specific aspect of the present invention, the instruction execution means checks whether or not a branch destination instruction is stored in the branch destination instruction storage means when a branch instruction occurs, and the branch destination instruction is If not stored, when the branch destination instruction is separated by the separating means and stored in the instruction storing means, it is also stored in the branch destination instruction storing means.

[0012]

When the branch instruction storage means is empty and the branch instruction is executed, the prefetch means prefetches a plurality of instructions from the beginning of the branch destination. This branch destination instruction is separated (predecoded) into an operation code and an operand by the separating means. Specifically, the separation is performed by identifying whether or not each 1 byte of the information read from the main storage device by the prefetch means is an operation code, and determining the instruction length of the peration code to determine the operand. Can be identified. The separated operation code and operand are paired and loaded into the instruction storage means. At the same time, these separated instructions are loaded into the branch destination instruction storage means together with the start address of the branch destination. As the branch destination instruction means, for example, an associative memory having a head address as a key may be used. In this way, the first few instructions at the branch destination are cached in the branch destination instruction storage means.

After that, when the branch instruction is executed, it is first compared whether or not the branch destination address is in the branch destination instruction storing means, and if the instruction starting from the address is cached, the branch destination instruction storing means. Is transferred to the instruction storage means. By executing the transfer of the branch destination instruction group from the branch destination instruction storage means to the instruction storage means at a time in block units, the processing speed of the branch instruction is further increased.
According to the present invention, the content of the branch destination instruction storage means has already been predecoded by the separation means, so that the pipeline type decoder can decode the instruction in a short time and waste of the pipeline due to the branch instruction. And the instructions can be executed at high speed.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram of an information processing apparatus which is a specific embodiment of the present invention. The embodiment shown in FIG. 1 comprises a central processing unit 1, a main memory 2 and a system bus 3.
Further, the central processing unit 1 includes an instruction prefetch unit 11, an instruction predecoder 12, an instruction prefetch buffer 13,
A branch target cache 15, a pipeline type decoder 16, and a pipeline type instruction execution unit 17 are provided.

In the present embodiment, it is assumed that the minimum unit of instruction is 1 byte, and an instruction set including instructions of three types of lengths of 1 byte, 2 bytes and 3 bytes is executed. FIG. 2 shows the format of the instruction in this embodiment. As shown in FIG. 2, the instructions of the present embodiment include 1-byte instruction having only the operation code, 2-byte instruction having the operation code and the operand A, and 3-byte instruction having the operation code and the operand A and the operand B. There are types. In any of these instructions, the operation code is 1 byte. The length of the instruction can be determined from this first 1-byte operation code. In this embodiment, the data width of the system bus 3 is 16 bits, that is, 2 bytes.

When the number of instructions stored in the instruction prefetch buffer 13 becomes smaller than a certain value, the instruction prefetch device 11 fetches 2 instructions from the main memory 2.
Read word (4 bytes), instruction predecoder 12
Pass to.

The instruction predecoder 12 discriminates, for each byte, whether or not it is an operation code of an instruction, and if it is an operation code, the kind of the instruction, and determines the length of the instruction. The operand portion is identified based on the determined length. In this way, the instruction predecoder 12 predecodes the fetched instruction, clarifies the configuration of the instruction, and stores it in the instruction prefetch buffer 13 as an operation code and an operand set corresponding thereto. At this time, the operation code is stored in the operation code storage unit 131, and the operand is stored in the operand storage unit 132.

The instruction prefetch buffer 13 is an 8-entry first-in first-out memory (FI).
FO), the operation code part 131 has an 8-bit width, and the operand storage part 132 has a 16-bit width.
Therefore, two operands in a 3-byte instruction can be stored in the same entry.

The branch target cache 15 includes an address storage unit 151 for storing a branch destination address (head address), an operation code storage unit 152, and an operation code storage unit 152.
The two-way set associative cache has an operand storage unit 132. It has 16 blocks of information sets (blocks) of the same capacity as the instruction prefetch buffer 13 (that is, 8 entries). Each block stores one branch destination instruction group. When the address of the branch destination of the branch instruction is hit, the block containing the hit operation code of the 16 blocks (sets) is transferred to the instruction prefetch buffer 13 from any block (set) of the cache by a dedicated transfer line. It can be loaded all at once via 14. Since this information is transferred block by block, it is performed at high speed.

The pipeline-type decoder 16 receives an operation code byte by byte from the operation code storage unit 131 of the instruction prefetch buffer 13 and decodes the operation code, thereby executing the pipeline-type instruction execution unit 17.
Pass to. The pipeline type instruction execution unit 17 includes a decoded instruction and an operand storage unit 1 corresponding to the instruction.
The instruction is executed using the operand from 32.

Next, the operation of this embodiment will be described. Immediately after the central processing unit 1 first starts operating, the instruction prefetch buffer 13, the data prefetch buffer 14, and the branch target cache 15 are empty. The instruction execution unit 17 requests the instruction prefetch device 11 to read an instruction from the main storage device 2. The instruction read by the instruction prefetch device 11 in response to the request is predecoded by the instruction predecoder 12. In the pre-decoding, whether or not it is the operation code of the instruction, and if it is the operation code, the type of the instruction is identified for each byte, and the length of the instruction is determined. The operand portion is identified based on the determined length. The operation code thus separated by the instruction predecoder 12 is the operation code storage unit 1 of the instruction prefetch buffer 13.
At 31, the operand is placed in the operand store 132. This operation is continued until the operation code is full in the instruction prefetch buffer 13.

The pipeline type instruction decoder 16 is
The operation code is received from the instruction prefetch buffer 13 byte by byte, decoded, and passed to the instruction execution unit 17. The pipeline-type instruction execution unit 17 executes the instruction using the decoded instruction and the operand from the data prefetch buffer 14. When the pipeline type instruction execution unit 17 executes instructions in this manner, the operation code stored in the instruction prefetch buffer 13 decreases. If the number of operation codes is less than a certain number, the instruction prefetch device 11 is requested to read an instruction. If there is no branch instruction, the instruction is processed as described above.

Next, the case where a branch instruction appears in the instruction flow will be described with reference to the flow chart of FIG. When a branch instruction occurs, it is first checked whether or not the instruction at the branch destination address is cached in the branch target cache 15. That is, when a branch instruction occurs (step 301), the instruction executing section 17 calculates the branch destination address of the branch instruction (step 302), and uses the calculated branch destination address as the branch target cache 1
Give to 5. The branch target cache 15 uses the function of the associative memory to execute the instruction execution unit 17
The branch destination address given from the address storage unit 15
1 is compared with the address stored in step 1 (step 30
3) The presence / absence of a branch destination address as a result of the comparison is returned to the instruction execution unit 17.

If the branch target cache 15 does not have the branch destination address, the instruction executing section 17 issues an instruction fetch request to the instruction prefetch unit 11 (step 308). The instruction prefetch device 11 prefetches the instruction at the branch destination address from the main storage device 2 (step 309) and, at the same time, clears all the entries in the instruction prefetch buffer 13. The prefetched instruction is then transferred to the instruction predecoder 12
Is pre-decoded by (step 310). The predecoded operation code and operand are newly stored in the operation code storage unit 131 and the operand storage unit 132 of the instruction prefetch buffer 13, and at the same time, one block (set) of the branch target cache 15 randomly selected. Is also stored (step 311). Even if the pipeline-type instruction decoder 16 starts decoding and the pipeline starts operating, the operation code storage unit 152 of the branch target cache 15 remains until one block (set) of the branch target cache 15 is full.
The operation code and the operand predecoded by the instruction predecoder 12 are also stored in the operand storage unit 153. In this way, the branch target cache 15 caches the instruction group starting from the start address of the branch destination.

When branching again to the address once branched by the branch instruction, the instruction prefetch unit 11 moves from the main memory 2 to the branch destination address because the branch target address is cached in the branch target cache 15. It is not necessary to prefetch a certain instruction, and it is sufficient to load all the operation codes and operand contents of the branch destination instruction group stored in the branch target cache 15 into the instruction prefetch buffer 13 and the data prefetch buffer 14 in block units. Good. If the instruction is cached in all the entries of the branch target cache 15 and a cache miss occurs due to the branch instruction, one entry of the branch target cache 15 is randomly selected and replaced with a new content.

In the present embodiment, the predecoded instruction is cached in the branch target cache 15 in advance, and when the branch target cache caches the branch target instruction when the branch instruction occurs, the branch target cache is cached. By inputting the operation code and operand of each instruction in pre-decoded form from 15 to the instruction prefetch buffer 13, the instruction decoding time is reduced, and the pipeline overhead due to the branch instruction and the instruction fetch waiting time are reduced. It can be reduced and instructions can be executed at high speed.

[0027]

As described above, according to the present invention, in an information processing apparatus for executing an instruction set composed of a plurality of types of instruction lengths by a pipeline method, a branch destination instruction storage means (branch target) is provided. Cache), predecoded instructions are cached in advance, and when the branch destination instruction storage means caches the branch destination instruction when the branch instruction occurs, the branch destination instruction storage means stores each instruction in the instruction prefetch buffer. By inputting the operation code and operand pair of an instruction in a pre-decoded form, the instruction decoding time is reduced and the pipeline overhead due to the branch instruction is reduced, so that the instruction can be executed at high speed. it can.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a diagram showing a format of an instruction in the embodiment.

FIG. 3 is a flowchart showing the operation when there is a branch instruction.

[Description of Codes] 1 ... Central processing unit, 2 ... Main memory unit, 3 ... System bus, 11 ... Instruction prefetch unit, 12 ... Instruction predecoder, 13 ... Instruction prefetch buffer, 15 ... Branch target cache, 16 ... Pipeline System instruction decoder 17 ... Pipeline system instruction execution unit.

Claims (9)

[Claims] 1. A prefetch means for prefetching at least one variable length instruction, a separating means for separating a variable length instruction prefetched by the prefetch means into an operation code and an operand, and a separating means for separating the operation code and the operand. Instruction storage means for temporarily storing at least one instruction consisting of an operation code and operand pair, instruction execution means for executing the instruction stored in the instruction storage means by a pipeline method, and execution by this instruction execution means An information processing apparatus comprising: a branch-destination instruction storage unit for separating at least one branch-destination instruction from among the instructions to be stored into an operation code and an operand and storing the branch-destination instruction together with the branch-destination address. 2. The information processing apparatus according to claim 1, wherein the prefetch unit collectively prefetches a plurality of variable length instruction groups at a time. 3. The separating means determines the instruction length of each instruction included in the instruction group prefetched by the prefetch means, identifies the operation code and operand of each instruction, and separates them. The information processing device according to claim 1. 4. The separation means determines the instruction length of each instruction included in the instruction group prefetched by the prefetch means, identifies the operation code and operand of each instruction, and separates them. The information processing apparatus according to claim 2. 5. A first-in-first-out memory having a capacity for storing a predetermined plurality of instructions each consisting of a set of operation codes and operands separated by the separating means is used as the instruction storage means. The information processing device according to claim 1. 6. The information processing apparatus according to claim 5, wherein the branch destination instruction storage means is an associative memory having a branch destination address as a key. 7. The instruction executing means, when a branch instruction is generated, checks whether or not the branch destination instruction is stored in the branch destination instruction storage means, and when the branch destination instruction is stored, 2. The information processing apparatus according to claim 1, wherein the instruction at the branch destination of the branch destination instruction storage means is transferred to the instruction storage means. 8. The instruction storage means has a capacity to store a predetermined plurality of instructions each consisting of a set of operation codes and operands separated by the separation means, and the branch destination instruction storage means has the instruction storage. It has a storage capacity capable of storing a plurality of blocks in the same instruction storage capacity as the predetermined instruction storage capacity of the means, and stores a branch destination instruction group in association with one branch instruction for each block. The information processing apparatus according to claim 7, wherein the transfer of information from the branch destination instruction storage means to the instruction storage means is performed at once in the block unit. 9. The instruction executing means checks whether or not a branch destination instruction is stored in the branch destination instruction storage means when a branch instruction occurs, and if the branch destination instruction is not stored, 2. The information processing apparatus according to claim 1, wherein when the instruction at the branch destination is separated by the separating means and stored in the instruction storage means, the instruction is also stored in the branch destination instruction storage means.