JPS61156363A - Data processing unit - Google Patents

Abstract

PURPOSE:To perform a processing of a large capacity of data at high speed and with many functions and purposes by plural processing units having an arithmetic function and changing over and connecting a data input and output to this processing unit. CONSTITUTION:An operation of processing units 32-35 is performed in such a manner that a data is inputted through a bus 41, passing through bus change over devices 36-40 is fed to processing units 32-35 and carries out a parallel processing by respective processing unit. By changing over the bus change over devices by a control signal 42 from a control device 31, the respective units 32-35 may be connected in series. The control device 31 performs a controlling for successively changing over the bus change over devices 36-40 in a period for processing one data, so that a data processing with many functions and with high speed is performed.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] This invention is a dual-sided processing device that operates at times as a dedicated processing device that performs large-capacity data processing such as image processing at high speed, and at other times as a general-purpose multifunctional processing device. The present invention relates to a data processing device having the following characteristics.

[Technical background of the invention and its problems]

Generally, a general-purpose computer system serving as a data processing device has one processing device or processing unit that performs calculations, excluding input/output devices and peripheral devices. Therefore, when the amount of human-powered data exceeds a certain value, even if a high-speed processing device is used, the processing time will be extremely long. Two methods are currently being used to solve these problems.

The first method is shown in Figure 2, and is based on the bus l
Processing unit 12゜1, t, which performs IC operation
14 and 15 to perform data processing on each processing unit.
) 12 to 15 in parallel.

In this case, if the processing units 12 to 15 have the same function, the same processing is performed in parallel (implemented) by each unit.

Furthermore, when the processing units 12 to 15 have different functions, the data to be processed is sent to the processing units 12 , 1.1 , 14 via each bus 11 .

15 are processed sequentially.

This method allows multi-functional processing. In this case, data is always input via the bus 11 to the processing unit 1 and processed. Therefore, even if the processing speed of the data processing unit is increased or the number of data processed is increased, it is dependent on and limited by the data transfer speed of the bus.

In addition, the second one is K as shown in FIG. 3, and the processing unit 2
2.23, 24.25 are connected in series and data processing is performed sequentially.

The data processed by the processing unit 22 passes through the bus 26 and is processed by the next processing unit 23. Next, the data is processed by the Nonosu 27, the processing unit 24, the Nonosu 2B, and the Processing N unit 25. It flows while being played.

Here, 21 is a control unit that controls each of the processing units 22 to 25, and performs timing control such as data flow using a control signal 29.

This method is generally called the 4-line method, and is suitable for high-speed processing of certain fixed data, but has the disadvantage that it cannot be used for general-purpose, multi-functional data processing.

[Object of the Invention] The present invention was made in order to eliminate the above-mentioned conventional drawbacks, and an object of the present invention is to provide a data processing device that can process large amounts of data at high speed and in a multifunctional manner. With the goal.

[Summary of the invention]

In the data processing of the present invention, a plurality of processing units each having an arithmetic function are arranged.

Please use a bus switcher to switch data input/output to the
This is what I did.

[Embodiments of the invention]

Embodiments of the data processing apparatus of the present invention will be described below with reference to the drawings. Figure Rc1 is a schematic diagram showing the configuration of one embodiment.

In this 11th ffl, processing units 32 to 35 having arithmetic processing functions are arranged in a matrix, and a bus switch 36 is connected between the processing units 32 and 33 via a bus 41. and 34
A bus switch 37 is connected via a bus 41 between them.

Similarly, a bus switch 40, . 19 are connected. - A gas switch 38 is connected between the gas switch 36 and 40' and between 37 and 39.

In addition, each processing unit '32~35, bus switch 36~
40 are each controlled by a control signal 42 from a controller 31.

Next, the operation of the data processing apparatus of the present invention configured as described above will be explained. In one operation of the processing units 32-35, data is input manually via the bus 41, passes through the bus switchers 36-40, and is transferred to the processing units 32-''3.
5, and each processing unit performs parallel processing. This corresponds to the conventional parallel processing method] and performs multi-functional processing.

Further, by switching the bus switching devices 36 to 40 using the control signal 42VC from the iI controller 31, the processing units 32 to 35 can be connected in series. This is equivalent to performing data processing using the conventional no-blind method.

In this way, if the bus switchers 36 to 40 are arranged so that they can be switched and connected independently and in any direction,
It can perform versatile and multi-functional data processing, and
Dedicated high-speed data processing is also possible.

In addition, the controller 31 is switched to the bus switch 3 within the 1-4 processing period.
If control is provided to sequentially switch data 6 to 40, multi-functional and high-speed data 4 processing can be performed.

Note that the Day 4 switchers 36 to 40 are the Day 4 processing device @/C.
Depending on the extent to which the functions and performance provided can be expanded, the K may be connected to any number of processing units, such as simultaneous connection to each processing unit or connection to each processing unit individually.

In addition, the connection processing unit y),? 2 to 35 may be automatically switched to the K111 order, or may be switched and connected by an external instruction via the control unit y).

Further, the number of processing units and the number of bus switching devices can be arbitrarily set to two or more.

〔Effect of the invention〕

As described above, according to the D4 processing device of the present invention, a large number of processing units are organically and optimally connected by controlling the switching of the bus switch.
A large amount of data can be processed at high speed and with multiple functions and purposes.

[Brief explanation of the drawing]

FIG. 1 shows an embodiment of the data processing device of the present invention.
Figures 2 and 3 are system diagrams of conventional data processing methods, respectively. 31...controller, 32-35...processing unit,
36-40...Bus switch. Applicant's agent Patent attorney Takehiko Suzue, f10

Claims (1)

[Claims] Two or more processing units each having an arithmetic processing function, a plurality of bus switchers having data input/output connected to each processing unit via a bus, and controlling the operation of each processing unit. A data processing device comprising a controller that switches the bus switch and transfers data input/output to a predetermined processing unit as appropriate.