JPH04274547A - Data transfer system - Google Patents

Abstract

PURPOSE:To reduce the number of input-output pins of an LSI circuit by transferring data in plural installments. CONSTITUTION:A select signal is stored in a register 11 which is used for selecting data which can be divided into two parts and a selector 12 selects data to be transferred based on the select signal. Of the selected data, a higher- order bit group is selected by means of a selector 13. The higher-order bit group selected by the selector 13 and sent from an LSI circuit 10 is selected as the higher-order bit group of the selector-equipped register 17 of an LSI circuit 15. The data transfer of a lower-order bit group is carried out while the 1st control register 14 is reset. Similarly, the LSI circuit 15 stores the lower- order bit group of transferred data while a register circuit 19 is reset.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer system, and more particularly to a data transfer system for transferring data consisting of a plurality of bits between LSIs.

0002

2. Description of the Related Art Conventionally, data consisting of multiple bits was transferred at one time. A conventional data transfer system will be explained with reference to FIG.

Referring to FIG. 2, in the conventional system, data was transferred from the data output side LSI 20 to the data input side LSI 23 at one time. The data output side LSI 20 outputs 18-bit data from this LSI 20 and 2
It includes a selector 22 that selects data to be transferred consisting of parity bits, and a register 21 that stores a select instruction signal to the selector 22.

The data input side LSI 23 also includes a selector register 25 for selecting and storing data transferred from the LSI 20 and a register 24 for storing a strobe signal of the selector register 25.

A conventional system with such a configuration operates as follows. That is, first, the output side LS
A select signal from the selector 22 is strobed into the register 21 of the I20. In the next cycle, register 2
When the output of 1 selects data to be transferred in the selector 22, the selector 22 outputs data consisting of 18 data bits and 2 parity bits as output data of the LSI 20.

On the other hand, at this time, in the input side LSI 23,
When the output of the register 24 storing the strobe signal of the register with selector 25 becomes valid and the select signal of the register with selector 25 selects the transferred data, this select signal and the output of the register 24 cause the register with selector 25 to 2 for 18 data bits sent
The data with the bit parity bit added is strobed.

[0007] In this way, data transfer was realized without dividing the data. Such data transfer systems transfer data consisting of multiple bits at a time. Therefore, the number of LSI input/output pins for transfer is equal to the number of bits of transfer data. However, an LSI that uses a large number of input/output pins has a drawback in that it is not possible to secure enough input/output pins for transfer data.

[0008]

OBJECTS OF THE INVENTION An object of the present invention is to provide a data transfer system in which the number of input/output pins of an LSI used for transfer can be reduced by eliminating the above-mentioned drawbacks.

[0009]

SUMMARY OF THE INVENTION In the data transfer system according to the present invention, the data output side LSI circuit includes selection means for dividing and transmitting data consisting of a plurality of bits at least twice, and a first selection means for controlling the selection of the selection means. The data input side LSI circuit includes a selectable data storage means for receiving the data divided into at least two times and divided into the same number of times as the number of times of transmission, and selective storage in the data storage means. The present invention is characterized by comprising a second control means for controlling.

0010

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, an embodiment of the present invention will be described in detail with reference to the drawings.

Referring to FIG. 1, one embodiment of the present invention includes:
It includes a data output side LSI circuit (hereinafter referred to as output side LSI) 10 and a data input side LSI circuit (hereinafter referred to as input side LSI) 15.

The data output side LSI 10 includes a selector 12 that selects data to be transferred that can be divided into at least two categories output from the LSI 10, a register 11 that stores a selection instruction signal for this selector 12, and data from the selector 12. The first control register 14 includes a selector 13 that divides the register into two and selects one of them, and a first control register 14 that is set by a selection instruction signal when the selector 13 makes a selection and is reset at the next timing of its own set timing.

The data input side LSI 15 includes a register with a selector 17 that selects data transferred from the LSI 10 and stores the data that is divided into two, a register 16 that stores the strobe signal of this register 17, and a register with a selector 17 that selects the data transferred from the LSI 10. When selecting data sent from the second control register 19, which is set by the select signal and reset at the next timing of the set timing, the output of this register 19 is "1" and is stored in the register 16. When the strobe signal sent is valid, control is performed to store data consisting of 9 bits of transmitted data and 1 bit of parity bit into the upper group of register 17, and register 19 is set to “0”.
” and the strobe signal stored in the register 16 is valid, the control circuit 18 performs control to store data consisting of 9 bits of data sent out and 1 bit of parity in the lower group of the register 17. include.

Next, the operation of one embodiment of the present invention will be explained in detail with reference to the drawings. The whole process is cycle 1,
This will be divided into three cycles, cycle 2 and cycle 3, and will be explained in detail with reference to FIGS. 1 and 3.

[0015] In FIG. 3, the operations of the undescribed functional blocks maintain their previous state. First, let us assume a case where data of a higher group of data that can be divided into two is transferred. In the LSI 10, the select signal from the selector 12 is stored in the register 11 in cycle 1. At this time, if this select signal selects the data to be transferred, "1" is set in the first control register 14 by the select signal.

In cycle 2, the selector 12 selects data to be transferred based on the output of the register 11. 1st
Since the control register 14 of is set to “1”,
The selector 13 selects data corresponding to the upper bit group from among the two pieces of data selected by the selector 12 that can be divided into two. This selection result is given from the output side LSI 10 to the input side LSI 15.

On the other hand, in the input side LSI 15, cycle 1
, the strobe signal of the register with selector 17 is stored in the register 16. In response to the select signal, the register with selector 17 selects the transferred data. At the same time, the selector signal sets the second control register 19.

In cycle 2, when the second control register 19 is being set and the strobe signal of the register 16 is valid, the upper bit group of the data sent from the output side LSI 10 is transferred to the upper bit group of the register with selector 17. Selected. These processes realize the transfer of the upper bit group of data.

Next, data transfer of the lower bit group will be explained in detail. In cycle 2, the output side LS
At I10, the first control register 14 set in cycle 1 is reset.

In cycle 3, the selector 12 selects transfer data in response to the select signal from the register 11. Further, while the first control register 14 is being reset, the selector 13 selects the lower bit group of the data to be transferred output from the selector 12. The data of the selected lower bit group is sent to the input LSI 15 as data to be sent from the output LSI 10 .

On the other hand, in the input side LSI 15, cycle 1
The second control register 19 set in cycle 2
will be reset.

In cycle 3, when the register 19 is being reset and the strobe signal from the register 16 is valid, the lower bit group of the data from the output side LSI 10 is strobed to the lower bit group of the register with selector 17.

[0023] Through these processes, data transfer of the lower bit group is realized. In the above manner, output side L
The data to be transferred, which can be divided into two, output from the selector 12 of the SI 10, is divided into an upper bit group and a lower bit group, and is strobed twice to the selector register 17 of the input side LSI 15. As a result, data transfer is realized.

[0024]

[Effects of the Invention] When transferring data consisting of multiple bits, the present invention has the effect of reducing the number of input/output pins of an LSI used for transfer by dividing the data into two and transferring the data twice. There is.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an embodiment of the present invention.

FIG. 2 is a diagram showing a conventional example.

FIG. 3 is a diagram for explaining the operation of an embodiment of the present invention.

[Explanation of symbols]

10 Data output side LSI 11 Register 12,13 Selector 14 First control register 15 Data input side LSI 16 Register 17 Register with selector 18 Control circuit 19 Second control register

Claims (1)

[Claims] Claim 1: A data output side LSI circuit includes a selection means for dividing and transmitting data consisting of a plurality of bits at least twice, and a first control means for controlling selection of the selection means, and a data input side LSI circuit. The side LSI circuit includes selectable data storage means for receiving the data divided into at least two times and divided into the same number of times as the number of times of transmission;
A data transfer system comprising: second control means for controlling selective storage in the data storage means.