JPH0334648A - Method of interconnecting computers - Google Patents

Abstract

PURPOSE: To attain the high speed of data transfer by constituting a control logic of a register and a logical gate, and establishing the interconnection in response to a request in an actual data system. CONSTITUTION: At the time of the control of data transfer in each computer 3, a control logic 5 decides whether or not received data should be preserved based on its own state and received data 6. Moreover, the control logic 5 decides which of received data 6, 12, 13 and data 11, 12, and 13 from the control logic 5 should be transferred 14 and 6 to the next adjacent computer 3 based on a successively generated clock pulse 2 based on its own state and the received data 6. Thus, data transfer between two computers can be attained at a high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Field of Application) The present invention relates to a method for interconnecting computers that enables high-speed data transfer between computers interconnected in a ring.

BACKGROUND OF THE INVENTION Many tasks handled by computers are most efficiently handled by coupling several computers together so that each computer handles subtasks.

Many known computer systems are based on interconnecting a large number of computers by using separate data channels between each two computers. Therefore, each computer has a fixed number of data channels to other computers in the system. These data channels allow data to be transferred from one computer to another, with some systems allowing data to be transferred in only one direction and other systems allowing data to be transferred in both directions. . Various topologies are used in building computer systems based on data channels between computers.

An overview of commonly used topologies can be found in the periodical “5c
ientific American (October 1987, pages 51 and 134).

One of these topologies is the IEEE Standard 802.5 “IBM Token-Ring Network (IBM
``Token-Rlng Network)'' where all the computers are interconnected in a ring, each computer having a data channel to each of its two neighbors, and a data channel from one neighbor to the other. It is possible to receive data and transfer data to another adjacent computer. To process data transfers synchronously, certain special data elements, "tokens," are circulated from computer to computer. When a computer transfers data to another computer, the computer first listens for this special data element, transfers the data including the address to the receiving computer, and then outputs the element. After the data is received, that particular data element will be circulated again.

To avoid having too many data channels in a system, it is necessary to be able to use a computer for passing data. When a computer transfers data, it will typically be the case that the data must be transferred through various other computers before it reaches the desired computer. A problem with existing data systems is that the data channel populations/outlets for each computer are independent in relation to each other. Thereby, data transfer through one computer can cause significant time delays in that data is received from one data channel and then has to be moved to the other data channel in order to be transferred again. become.

In addition, in that system, synchronization processing of data transfer is another problem. Complex topologies often result in complex synchronization processes to avoid collisions on a data channel and to achieve optimal data flow on that channel. Additionally, this introduces additional time delays in the system and makes the system expensive.

As mentioned above, the problem of synchronization in the IBM Token-Ring Network is solved by cycling special data elements.

However, this solution also introduces a relatively large time delay at each computer due to the data that must pass through.

In the "IBM-Kunling Network", only two computers can communicate at the same time,
The average waiting time for data transfer to start is
Even when the state of no data transfer continues, it remains relatively large.

SUMMARY OF THE INVENTION By interconnecting computers in accordance with the method described in this invention, data transfer between two computers can be performed very quickly.

The transfer of data through a computer passes only through certain registers, thereby causing the transfer of data to occur in progressions of clock cycles. Computers that are interconnected may be physically organized so that the conduits for data transfer are short. This would greatly reduce the time required to move data from one computer to its neighbor.

This is particularly advantageous where new electronic components introduce conduit delays. That is, the path of transfer will constitute a significant portion of the time consumption. The method according to the invention is simple and reasonable to implement, and also allows a large number of computers to communicate with each other synchronously.

The invention is implemented in that each computer has a data channel for receiving data and a data channel for transferring data. Each data channel consists of a number of bits. The input data channel is connected to a multiplexer and control logic that can capture and record incoming data and detect certain incoming data values. The output of the multiplexer is connected to the register consisting of a D-flip-flop,
The exit of this register leads to a data channel for transferring data. The output data channels are also connected to input data channels of other computers. Furthermore, all data channels are coupled in this way, so that the data channels are coupled in a ring. The multiplexer has two populations, one of which is connected to the input data channel, as described above. The other inlet is connected to the outlet of the control logic and is used when data from one computer has to be transferred to another computer.

The control logic consists of registers and logic gates.

These interconnections are made in accordance with the requirements of the actual data system. Furthermore, the control logic is also connected to the rest of the computer, consisting of data components such as processors, storage circuits, local output gates, and the like. Furthermore, the system has a common tarok oscillator connected to every computer. For each computer, the clock signal from this clock oscillator controls the registers to the output data channels and controls the control logic. to be processed synchronously.

(Example) Hereinafter, one embodiment of the present invention will be described based on the drawings.

FIG. 1 is a block diagram showing a computer system, FIG. 2 is a block diagram showing main parts of each computer embodying the present invention, and FIG. 3 is a block diagram showing control logic in each computer in more detail. It is.

Data transfer is synchronously processed by a clock oscillator 1, which is coupled 2 so that each computer 3 can receive a clock signal from the clock oscillator 1 as simultaneously as possible with an adjacent computer. To avoid noise in the clock signal,
The same is the termination 4 on the opposite side from the clock oscillator 1.

With each clock cycle, each computer 3 transfers a data element via the data channel 6 to the control logic 5 of an adjacent computer. Data elements in the data channel 6 include control data 6a, address 6b, and
The data to be transferred is divided into 6C. Control data 6a
(1 bit) clearly states whether the remaining data 6b, 6c are valid or not, in other words, whether or not these data are in the process of being transferred to a certain computer 3. If these data are invalid, any computer 3 can replace them with valid data. Address 6b (8 bits) declares which computer is to receive the data. Data 6C is the identifier of the computer to be transferred;
It consists of a number (8 bits) and information to be transferred (32 bits).

Illegal data elements are continuously transferred between computers unless data transfer occurs between computers. Whenever one computer 3 wants to transfer data to another computer, a command is sent to the data bus 7.
first, the computer 3 to be received.
address 7a is set in register 8. Then,
The data 7a to be transferred is set in the buffer register 9, and the control unit 10 sets the data 7a in the transfer state.
Set by b. The control unit 10 listens for illegal data elements and immediately receives them. Then, the data 11 consisting of the control data 11a1 address 11b1 and the data 11c to be transferred is transferred to the register population 13 through the multiplexer 12, and transferred to the data channel 6 through the base register 14 with the subsequent clock pulse. be done. In particular, the data 11c being transferred includes the identifier of the computer 3 to which it is being transferred, in addition to the data itself. The control unit 10 then signals the data bus 7b that further data is ready to be transferred.

To receive data, each computer 3 continuously checks the input data channel. That is, the control unit 10 checks whether the control data 6a is valid, and the comparator 15 checks whether the address 6b is equal to the fixed address of the computer appearing in the register 16.

If both these checks are positive, the input data 6c is recorded in the FIFU-register 17, and the control unit 10 also sets the data 11c to be invalid and sets the invalid data 11c on the subsequent clock pulse. is transferred to data channel 6 through base register 14.

The control unit 10 then provides a signal over the data bus 7b on which the data was received. Here, FIFU
- The upper data word in register 17 contains, in addition to the transferred information, the identifier of the transferring computer.

Each computer 3 has relatively small electronics depending on the clock frequency, for example a multiplexer 1.
2, base register 14, FIFU-register 17,
A comparator 15 and a control unit 10 are incorporated. If the conduit 6 between the computers 3 is relatively short, the frequency of the clock oscillator 1 can be set high without increasing cost or power consumption. By setting the frequency of the clock oscillator 1 to different times faster than the frequency of the data bus 7, further combinations of computers 3 can be communicated simultaneously without introducing any delay. If the frequency of the clock oscillator 1 is equal to the frequency of the data bus 7, then two average sets of computers 3 will be able to communicate simultaneously without delay.

(Effects of the Invention) As explained above, according to the present invention, data can be transferred at high speed between computers interconnected in a ring, and a large number of computers can communicate with each other in synchronization. It has the effect of being able to.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a computer system; FIG. 2 is a block diagram showing main parts of each computer embodying the present invention; FIG. 3 is a block diagram showing the control logic in each computer in more detail. It is. DESCRIPTION OF SYMBOLS 1... Clock oscillator, 3... Computer, 6... Data channel, 1 12... Multiplexer, 1 14... Base register. 2... Clock pulse, 5... Control logic, 1... Data, 3... Register Okawa,

Claims (3)

[Claims] (1) Multiple computers (3, 3...) where each computer (3) has two adjacent computers (3, 3)
The clock pulses (2) are transmitted in parallel to the circularly coupled computers (3) by the clock oscillator (1), and based on each clock pulse (2), one of the Adjacent computer (3)
receives a fixed number of bits in parallel from the other adjacent computer (3) based on each clock pulse (2).
) in parallel and the control logic (5) based on its own state and the received data (6) decides whether to save the received data or not. In the computer interconnection method, the data transfer in each computer (3) is controlled so that the control logic (5) determines whether the received data should be stored or not, and at the same time Data (6
, 12, 13) or the data (11, 12, 13) from said control logic (5) are transferred (14, 6) to the next adjacent computer (3) based on subsequent clock pulses (2). A method for interconnecting computers, characterized in that the control logic (5) also determines whether the computer should be connected. (2) Define which computer has transferred the actual data using the parallel data (6c) being transferred between the computers (3), and define which computer has transferred the actual data (
2. A method for interconnecting computers according to claim 1, wherein the computer (3) identifies which computer (3) has transferred the actual data. (3) The clock pulse (2) is a computer (3)
Said data transfer (6) by means of a clock oscillator (1) coupled (2) in two passes along a ring of rings and together at opposite ends of the ring to form a termination (4).
3. The method for interconnecting computers according to claim 1, further comprising performing synchronous processing on the computers.