KR100356918B1 - Output Port Availability Recognizer for an Interconnection Network with Asynchronous Ports and Method of recognizing the same - Google Patents

Abstract

The present invention provides an apparatus comprising: first means for outputting a first logic signal in accordance with a clock signal and a first signal output from a packet transmitter and initialized by a reset signal; Second means for controlling passage of a second signal output from an interconnection network in accordance with the first logic signal; Third means for synchronizing a signal output from the second means according to the clock signal; Fourth means for storing a signal synchronized by said third means at a previous clock and outputting a stored signal; Fifth means for detecting a transition state of the second signal by using a signal output from the third means and a signal inverted from the fourth means; And a sixth means for outputting a signal output from said fifth means, a signal thrust from said third means, and a signal for determining availability of an interconnection network output port using said first signal. We present an output port availability recognizer that can recognize the availability of interconnect network output ports quickly and efficiently with minimal overhead to increase port utilization, reduce packet transmission latency, and increase data rates.

Description

Output port availability recognizer for an interconnection network with asynchronous ports and method of recognizing the same

The present invention relates to a parallel computer system and to an interconnection network. Specifically, the present invention relates to network port control for packet transmission in each node in a parallel computer system in which several nodes are connected through an interconnection network. It relates to an availability recognizer.

A parallel computer system refers to a computer system in which a plurality of nodes exchange information through an interconnection network to perform jobs and tasks in cooperation with each other. In a parallel computer system, each node exchanges information over an interconnection network, so the transmission latency and bandwidth between nodes greatly influence the performance of the parallel computer system. considerations).

The interconnection network has been actively researched and devised in various design perspectives and is effectively used in parallel computer systems. Interconnect network port control at each node should be designed to minimize transmission latency and provide high data rates in packet transmission.

Ports of the interconnection network may have a synchronous interface or an asynchronous interface depending on the implementation method. The synchronous port uses the same clock domain for both nodes and interconnection networks, so port control is simple and the availability of the port can be easily recognized by control signals.

On the other hand, asynchronous ports use different clocks for nodes and interconnection networks, so the interface must be designed asynchronously. In other words, a complex port interface must be placed between the node and the interconnection network, and a device that recognizes the availability of the port quickly and safely with a minimum of overhead is required.

IBM's DL Garmire et al. Invented a self-timed interface for use in large parallel systems (see DL Garmire, et al., “Self-timed interface for a network of computer processors interconnected in paralled,” United States Patent, No. 5694612, December 2, 1997.). Self-synchronizing interfaces carry serial data on parallel buses and simultaneously transmit clock signals separately. The receiving side electrically and securely receives the parallel data using a separately transmitted clock signal. This minimizes the effects of system performance limitations such as bus length and system clock speeds, enables the high-speed transfer of digital data over parallel buses, resulting in a scalable interconnect suitable for parallel computer systems. It becomes possible.

Compared to the conventional invention, the present invention proposes a controller and method for recognizing the availability of an asynchronous output port that is not self-synchronizing, and minimizes the availability of the output port by using a pass control module and a availability detection module including a finite state machine. It can be recognized quickly and efficiently with the overhead of.

While the prior art is limited to port control in an interconnection network with a synchronous port or has a separate packet synchronizer between the node and the interconnection network, the present invention is directed at a node connected to an interconnection network having an asynchronous port. By quickly and efficiently recognizing the availability of the interconnect network output ports, it is possible to minimize packet transmission latency and maximize port utilization, resulting in reduced data transmission time and increased data rates.

Accordingly, an object of the present invention is to transmit a packet through an interconnection network with asynchronous ports in a parallel computer system composed of multiple nodes, The present invention provides an output port availability recognizer that recognizes the availability of an asynchronous network output port. Another object of the present invention is to recognize the availability of the output port of the interconnection network with a minimum of overhead (maximum overhead) to maximize the port utilization, minimize the transmission delay of the packet and increase the transmission rate and the recognition thereof To provide a method.

The output port availability recognizer according to the present invention for achieving the above object comprises: first means for outputting a first logic signal in accordance with a clock signal and a first signal output from a packet transmitter and initialized by a reset signal; Second means for controlling passage of a second signal output from an interconnection network in accordance with the first logic signal; Third means for synchronizing a signal output from the second means according to the clock signal; Fourth means for storing a signal synchronized by said third means at a previous clock and outputting a stored signal; Fifth means for detecting a transition state of the second signal by using a signal output from the third means and a signal inverted from the fourth means; And a sixth means for outputting a signal outputted from the fifth means, a signal thrusted from the third means, and a signal for determining the availability of the interconnection network output port using the first signal. .

According to another aspect of the present invention, there is provided a method for recognizing an output port availability, comprising: outputting a first logic signal according to a clock signal and a first signal output from a packet transmitter by a pass control module initialized by a reset signal; Controlling the passage of the second signal output from the signal interconnection network by the first AND gate in accordance with the first logic; Synchronizing a plurality of flip-flops with a signal output from the first AND gate according to the clock signal; Outputting the stored third signal after the last flip-flop stores a value in a clock cycle immediately before the output signal through a synchronization process; Outputting a fourth signal by detecting a transition state of the second signal using a signal outputted through a synchronization process in the last flip-flop and a signal inverted from the third signal; And an availability detecting module outputting a signal for determining availability of an interconnection network output port using the fourth signal, a signal output through a synchronization process in the last flip-flop, and the first signal. .

1 is a connection diagram of a node and an interconnection network through separate input and output ports.

2 is a block diagram of an output port availability recognizer in accordance with the present invention.

3 is a state transition diagram of a pass control module.

4 is a state transition diagram of the availability detection module.

<Description of Signs of Major Parts of Drawings>

100: interconnection network 101, 102, 103 and 104: node

101A, 101B, 102A, 102B, 103A, 103B, 104A and 104B: I / O ports

230: pass control module

241 and 245 AND gates 242, 243 and 244 flip-flop 250 availability detection module

The present invention provides the availability of an asynchronous interconnect output port at each node of a parallel computer system in which multiple nodes are connected through an interconnect network with asynchronous ports. Output port availability recognizer. An object of the present invention is a parallel computer system in which a plurality of nodes can be connected to an interconnection network.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

1 shows a parallel computer in which several nodes 101, 102, 103, 104 are connected to the interconnection network 100 through separate input / output ports 101A, 101B, 102A, 102B, 103A, 103B, 104A, 104B. It gives an overview of the system.

The output ports 101A, 102A, 103A, 104A are data paths for outputting packets from the respective nodes 101, 102, 103, 104 to the interconnection network 100, and the input ports 101B, 102B, 103B and 104B are data paths for entering packets from the interconnection network 100 to each node 101, 102, 103, 104.

2 shows the configuration of an output port availability recognizer which is a direct subject of the present invention.

The output port availability recognizer is a hardware device that exists inside each node 101, 102, 103, 104 and recognizes the availability of the output ports 101A, 102A, 103A, 104A connected to the interconnection network 100. . The output port availability recognizer has four input signals 201, 202, 203, 204 and one output signal 221. Inside the output port availability recognizer is a pass control module 230, two AND gates 241 and 245, three flip-flops 242, 243 and 244 and an availability detection module. module 250).

The four signals input to the output port availability recognizer are the VALID signal 201, the READY signal 202, the CLOCK signal 203, the RESET # signal 204, and the like. The VALID signal 201 is a signal input from a packet sender in a node. A VALID signal 201 indicates that a packet transmitter transmits a packet to an output port. The READY signal 202 is an asynchronous signal input from the interconnection network and should be used after going through a synchronization process. In addition, the READY signal 202 is an edge-sensitive signal, which indicates that when the READY signal 202 transitions from 0 to 1, the interconnect network is ready to receive packets from the node, and the interconnect network from the node. When one packet is transmitted, the READY signal 202 transitions from 1 to 0 after a predetermined time has elapsed. The CLOCK signal 203 is a clock signal used for all synchronous circuits of the port availability recognizer. The RESET # signal 204 is a signal for initializing the port availability recognizer. If the RESET # signal 204 is 0, the port availability recognizer is initialized, and if 1, the port availability recognizer is in a normal operation state.

The PORTRDY signal 221 output from the port availability recognizer is a signal driven by a packet transmitter in a node. If the PORTRDY signal 221 is 1, the interconnect output port is in an available state, and if it is 0, it is not in an available state. Indicates. The packet transmitter may transmit one packet to the interconnection network when the PORTRDY signal 221 is 1, and may not transmit the packet when the PORTRDY signal 221 is 1.

Pass control module 230 controls whether to pass the READY signal 202 into the output port availability recognizer. The PASS signal 211 output from the pass control module 230 is a control signal for determining the pass of the READY signal 202. The pass control module 230 is a synchronous circuit initialized by the RESET # signal 204 and operated by the CLOCK signal 203. If the RESET # signal 204 is 0, the pass control module 230 drives the PASS signal 211, which is an output signal, to 1.

The front end AND gate 241 passes the READY signal 202 when the PASS signal 211 is 1 and does not pass when the PASS signal 211 is 0. That is, if the PASS signal 211 is 1, the value of the READY signal 202 is displayed in the RDYP signal 212 as it is. If the PASS signal 211 is 0, the RDYP signal 212 is correlated with the value of the READY signal 202. 0 without.

Two flip-flops 242 and 243 connected in series at the output of the front AND gate 241 are responsible for performing the synchronization process, and the first flip-flop 242 latches the RDYP signal 212. The latch outputs the RDYL signal 213, and the second flip-flop 243 latches the RDYL signal 213 to output the RDYDL signal 214. The following flip-flop 244 checks whether the READY signal 202 has transitioned from 0 to 1, and checks the value in the prior clock cycle of the RDYDL signal 214 outputted through the synchronization process. The stored value is output as the RDYTL signal 215.

The rear AND gate 245 directly performs a function of checking whether the READY signal 202 has transitioned from 0 to 1, and irradiates the RDYDL signal 214 and the RDYTL signal 215 output through the synchronization process. That is, when the value of the RDYTL signal 215 is 0 and the value of the RDYDL signal 214 is 1, the LO2HI signal 216 which is the output of the rear AND gate 245 becomes 1, otherwise it becomes 0. The RDYTL signal 215 is inverted as shown in FIG. 2 and input to the rear AND gate 245.

The availability detection module 250 performs the final step of recognizing the availability of the interconnect network output port and detects the availability of the output port with reference to the VALID signal 201 and the RDYDL signal 214 and the LO2HI signal 216. The available state of the output port is driven to the packet transmitter in the node via the PORTRDY signal 221, which is an output signal. The availability detection module 250 is a synchronous circuit initialized by the RESET # signal 204 and operated by the CLOCK signal 203. If the RESET # signal 204 is 0, the availability detection module 250 drives the PORTRDY signal 221, which is an output signal, to one.

3 and 4 illustrate state transitions within the pass control module 230 and the availability detection module 250, respectively.

In FIG. 3 and FIG. 4, circles represent respective states, and the notation in a circle represents a state name. The arrows connecting the states indicate the direction of the state transitions, and the notation on the arrows indicates the conditions of the state transitions. No marking on the arrow indicates transition to the direction of the arrow at the next clock. State transition occurs at the rising edge of the CLOCK signal 203, which is a clock signal.

3 illustrates a state transition inside the pass control module 230. The initial state of pass control module 230 is IDLE state 301. That is, when the RESET # signal 204 is 0, the pass control module 230 is in the IDLE state 301. In the IDLE state 301, the PASS signal 211, which is the output of the pass control module 230, is driven to 1 to pass the READY signal 202 into the output port availability recognizer. If the VALID signal 201 is 0, it transitions to the WAIT state 302, and if 1, the IDLE state 301 is maintained.

The PASS signal 211 is driven to 1 even in the WAIT state 302. If the VALID signal 201 is 1, it transitions to the ONE state 303, and if 0, the WAIT state 302 is maintained. In ONE state 303, TWO state 304, THREE state 305, FOUR state 306, and FIVE state 307, a state transition occurs at the next clock without conditions, and the PASS signal for five clock cycles. Drive 211 to zero so that the READY signal 202 does not pass through the output port availability recognizer.

4 illustrates a state transition inside the availability detection module 250. The initial state of the availability detection module 250 is an IDLE state 401. That is, if the RESET # signal 204 is zero, the availability detection module 250 is in the IDLE state 401. In the IDLE state 401, the availability detection module 250 drives the PORTRDY signal 211 as an output to 1 to inform the packet transmitter in the node that the interconnect network output port is available. In the initial state, the interconnection network can receive one packet. If the VALID signal 201 is 1, it transitions to the WAIT state 402, and if 0, the IDLE state 401 is maintained.

In the WAIT state 401, the PORTRDY signal 221 is driven to zero to inform the packet transmitter in the node that the interconnect output port is not available. If LO2HI signal 216 is 1, it transitions to SYNC state 403; if 0, WAIT state 402 is maintained.

In SYNC state 403, the PORTRDY signal 221 is driven to 1 to inform the packet transmitter in the node that the interconnect network output port is available. If the RDYDL signal 214 is 0, it transitions to the WAIT state 402, and if it is 1, the SYNC state 403 is maintained.

As described above, the present invention invents an output port availability recognizer that recognizes the availability of interconnection network ports in each node of a parallel computer system connected by an interconnection network having an asynchronous port, which increases port utilization and packet transmission. In order to reduce latency and increase the transmission rate, we propose an efficient device and its operation that the interconnect output port recognizes availability quickly and effectively with minimal overhead.

As described above, the present invention is an apparatus for recognizing the availability of the interconnection network output port in each node of a parallel computer system in which several nodes are connected through the interconnection network having an asynchronous port. The invention invents a recognized output port availability recognizer. The present invention recognizes the availability of interconnect network output ports quickly and efficiently with minimal overhead in a node connected to an interconnection network having an asynchronous port, thereby increasing port utilization, reducing packet transmission latency and increasing transmission rate. Get That is, it contributes to the overall performance of parallel computer systems connected by interconnection networks with asynchronous ports.

Claims (9)

First means initialized by a reset signal and outputting a first logic signal in accordance with a first signal output from a clock signal and a packet transmitter; Second means for controlling passage of a second signal output from an interconnection network in accordance with the first logic signal; Third means for synchronizing a signal output from the second means according to the clock signal; Fourth means for storing a signal synchronized by said third means at a previous clock and outputting a stored signal; Fifth means for detecting a transition state of the second signal by using a signal output from the third means and a signal inverted from the fourth means; And a sixth means for outputting a signal for determining the availability of the interconnection network output port using the signal output from the fifth means, the signal output from the third means, and the first signal. Output port availability identifier for interconnection networks with asynchronous ports. The method of claim 1, And said second means comprises an end gate. 10. An output port availability recognizer for an interconnection network having an asynchronous port. The method of claim 1, And said third means consists of a plurality of flip-flops connected in series with each other. The method of claim 1, And said fifth means comprises an end gate. 10. An output port availability recognizer for an interconnection network having an asynchronous port. The method of claim 1, And said first means comprises a pass control module. The method of claim 1, And said sixth means comprises an availability detection module for detecting the availability of an interconnection network output port. Outputting, by the pass control module initialized by the reset signal, a first logic signal according to a clock signal and a first signal output from the packet transmitter; Controlling the passage of the second signal output from the signal interconnection network by the first AND gate in accordance with the first logic; Synchronizing a signal output from the first AND gate by a plurality of flip-flops according to the clock signal; Outputting the stored third signal after the last flip-flop stores a value in a clock cycle immediately before the output signal through a synchronization process; Outputting a fourth signal by detecting a transition state of the second signal using a signal outputted through a synchronization process in the last flip-flop and a signal inverted from the third signal; And an availability detecting module outputting a signal for determining availability of an interconnection network output port using the fourth signal, a signal output through a synchronization process in the last flip-flop, and the first signal. Output port availability recognition method for interconnection network with asynchronous port. The method of claim 7, wherein The state transition of the pass control module transitions to the WAIT state when the VALID signal is 0 in the IDLE state, and maintains the IDLE state when the pass control module is 1; Transitioning to the ONE state when the VALID signal is 1 in the WAIT state, and maintaining the WAIT state when the VALID signal is 1; A method for recognizing output port availability for an interconnection network with an asynchronous port characterized by a state transition at the next clock without conditions in the ONE state, TWO state, THREE state, FOUR state, and FIVE state. The method of claim 7, wherein The state transition of the availability detection module Transitioning to the WAIT state if the VALID signal is 1 and maintaining the IDLE state if 0; Transitioning to a SYNC state when the fourth signal is 1 in the WAIT state and maintaining a WAIT state when the fourth signal is 0; An output port for an interconnection network having an asynchronous port, comprising: translating the last flip-flop in the SYNC state to a WAIT state when the output signal is 0 and maintaining a SYNC state when 1 Availability awareness method.