JPH04138555A - Parallel type digital signal processor - Google Patents

Abstract

PURPOSE:To reduce the number of lines constituting an instruction bus while maintaining easiness for the sending of an instruction signal by adding an identification(ID) means for indicating which digital signal processor(DSP) is to be driven to an instruction signal and providing plural DSPs with respective recognizing means for recognizing the ID means. CONSTITUTION:When an instruction signal and an ID signal are outputted from a CPU 10, a recognizing circuit in each DSP inputs the ID signal consisting of upper 4 bits to a register 26 and inputs the instruction signal consisting of the 5th bit or less to a register 22. Whether the ID signal inputted to the register 26 instructs the start of operation of its own DSP or not is decided by a decoder 28, and at the time of deciding that the operation start of its own DSP is instructed, the decoder 28 instructs the DSP to transfer the instruction signal stored in the register 24 to the inside of the DSP and the DSP starts operation based upon the contents of the instruction signal. Thus, the instruction signal is transmitted from the CPU to respective DSPs through one instruction bus while maintaining the simpleness of a transmission procedure.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention enables tasks to be performed by multiple digital signal processing processors connected in parallel when executing a very long program or performing a huge amount of calculation. The present invention relates to a parallel digital signal processing device that is capable of processing data at high speed by sharing the functions.

[Conventional technology]

FIG. 5 is a block diagram of an example of a conventional parallel digital signal processing device. In the figure, a central processing unit N (hereinafter also referred to as CPU) 10 is a digital signal processing processor (hereinafter also referred to as DSP) which may consist of a single CPU or multiple CPUs.
'12't~12, data bus 14 and instruction bus 1
6, it is connected in parallel with CPU10. Furthermore, a data store 18 is connected to the data bus 14 to temporarily store data to be transferred. DSP12
．． ~12. has an internal decoder, memory, and logic circuit, and decodes instructions supplied from the CPU I O through an instruction bus 16, and performs arithmetic processing on data sent through a data bus 14.

Data is transferred from the CPU I O to each DSP via the data store 18. For example, when transferring certain data from CPU10 to DSP12+, CPU
l0 provides the data on data bus 14 for temporary storage in data store 18. The DSP 12+ is then commanded via the instruction bus to access the data store 18 and read the data from the data store 18 to the DSP 12+. The same applies when data is transferred from CPU10 to another DSP.

Transfer of data between DSPs is also performed via the data store 18. For example, if another DSP 12g requires data obtained through arithmetic processing in the DSP 12, the CPU 10 first transfers the data to the DSP 12. 12 + to store its data in data store 18 over data bus 14. After that, DSP
1.2 Command z to access data store 18 and read this data from data store 18. In this way, DSPI2. Data is transferred from the DSP 12t to the DSP 12t.

By the way, when an instruction bus is connected in parallel from the CPU to each DSP, the word length of the instruction signal output from CPU10 is equal to the sum of the word lengths of the instruction signals supplied to each DSP. That is, the word length of the instruction for the DSPI 21 is n, the word length of the instruction for the DSPI 22 is nz, .
...If the word length of the command for DSPI2 is n, then
The word length N of the instruction supplied from the CPU 10 is N=Σn8.If the instruction signals for each DSP are all n bits equally, the number of bits of the entire instruction signal supplied from the CPU is nxm bits. .

In this way, the word length of the command signal output from the CPU is
If the sum of the word lengths of the command signals for the SP is used, high-speed processing becomes possible and the procedure for transferring the command signals from the CPU to the DSP becomes easy.

[Problem to be solved by the invention]

However, in the conventional parallel digital signal processing device as described above, the number of command bus lines for transmitting command signals increases, which is undesirable in terms of hardware configuration. In particular, CPtJ using existing communication lines
If an attempt is made to send a command signal from the DSP to the DSP, various inconveniences will occur.

In addition, when each DSP and CPU are connected with one instruction bus, even if you want to give the same instruction to multiple DSPs, you can specify each DSP one by one on the CPLI side and send multiple instructions in order. The instructions must be sent in batches, which complicates the operation of the CPU and
There is a problem in that it takes time to transmit commands.

The present invention has been made based on the above circumstances, and provides a parallel digital signal processing device that can reduce the number of lines constituting an instruction bus while maintaining the ease of sending instruction signals from a CPU to a DSP as in the past. The purpose is to provide the following.

[Means to solve the problem]

To achieve the above object, the present invention connects a central processing unit and a plurality of digital signal processing processors through a data bus and an instruction bus, and the plurality of digital signal processing processors connects a central processing unit and a plurality of digital signal processing processors based on instructions from the central processing unit. In a parallel digital signal processing device that performs parallel processing of data, an identification means for indicating which digital signal processing processor is to be operated in response to an instruction signal supplied from the central processing unit to the plurality of digital signal processing processors through the instruction bus. Additionally, the plurality of digital signal processing processors are further provided with recognition means for recognizing the identification means.

[Effect]

In the present invention, with the above configuration, when a command signal is output from the central processing unit (CPU), the recognition means provided in each digital signal processor (DSP) recognizes the content of the identification means added to the command signal. As a result, when the identification means matches the signal set in each recognition means, the DSP starts operating and executes the contents of the command signal.

The identification means not only instructs the start of operation of a single DSP (but can also instruct the operation of any plurality of DSPs or all DSPs to start at the same time).In addition, the identification means is added to the command signal. With this configuration, the command signal can be a serial signal instead of a parallel signal, and an existing communication line with fewer lines can be used.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a block diagram of an embodiment of the present invention.
I is a diagram showing an example of the bit configuration of a command signal to which an identification bit (identification means) is added, and FIGS. 3 and 4 are for each DSP.
FIG. 2 is a circuit diagram showing an example of a recognition circuit provided inside.

In FIG. 1, the same components as those in FIG. 5 are denoted by the same reference numerals, and detailed explanation thereof will be omitted. In FIG. 1, unlike in FIG. 5, the bus width of the instruction bus 14 coming out from the CPU 10 is equal to the bus width of the instruction buses connected to each DSP 12+ to 12 degrees, and all of them are n bits. The command signal and identification signal sent to each DSP via the command bus 14 have a bit configuration as shown in FIG. 2, for example. In other words, the first 4 bits are identification bits that indicate which DSP starts operation, and thereby
Six types of combinations can be selected. The n-4 bits following the fifth bit are the contents of the command signal to the DSP.

The DSP can be selected not only by specifying one DSP one by one, but also by specifying a combination of a plurality of arbitrary DSPs. Naturally, if the number of identification bits is increased, the number of combinations of DSPs that can be specified also increases.

FIG. 3 is a circuit diagram of an example of a recognition circuit included in each DSP in FIG. 1, and the instruction system includes two registers 22 and 2.
4, and one register 26 and decoder 2 for the identification system.
8 is provided. This circuit is used when command signals are supplied in parallel through n-bit pass lines. When the command signal and identification signal are output from CPU10, the recognition circuit inside each DSP takes in the first 4-bit identification signal to the register 26, and at the same time inputs the first 4-bit identification signal to the register 26.
2, the command signal from the fifth bit onward is taken in.

A decoder 28 determines whether the identification signal taken into the register 26 instructs the start of the operation of its own DSP. At the same time, the command signal is transferred to the register 24.

When the decoder 28 determines that this identification signal is an instruction to start the operation of its own DSP, the decoder 28 instructs to transfer the command signal stored in the register 24 to the inside of the DSP. Starts an operation according to the contents of the command signal. On the other hand, when the decoder 2 determines that the identification signal does not instruct the start of operation of its own DSP, it instructs the register 24 not to send the command signal stored here to the next stage, and executes the DSP. is not started.

FIG. 4 is a diagram showing an example of a recognition circuit when command signals and identification signals from the CPU are supplied as temporally serial signals. Identification signal and command signal are clock signal C
It is serially supplied from the input terminal in synchronization with K, and is shifted to the right one bit at a time in synchronization with clock signal CK while being held in a flip-flop (FF). Therefore, the number of FFs is n, which is the same as the number of bits of the instruction bus.

As above, the first 4 pins of the command signal are the DSP
If one identification signal and one command signal are all held FF, the four identification signals on the right side are held OFF. In this state, the outputs of these four FFs are combined with a preset value as a signal indicating this DSP and four two-manufactured AND gates 30. ~30
Compare by 4.

Here, when the identification signal matches this preset signal, the output of the four-man power AND gate 32 becomes high level, and at this time, the two-man power AND gate 34. -34□ supply the signals of each focus from the 5th bit onward, that is, the command signal for the DSP, to the register 36 as they are. This causes the DSP to start executing in accordance with the contents of this command signal.

On the other hand, when the identification signal does not match a preset signal, the output of the four-man power AND gate 32 becomes a low level, and the output of the two-man power AND gates 341 to 34R-4 remains at a low level regardless of the contents of the command signal. All are at low level. Therefore, the contents of the command signal are not transmitted to registers 36 and beyond, and execution of this DSP is not started.

In this embodiment, the case where the identification signal is 4 bits has been described, but the present invention is not limited to this, and it goes without saying that identification signals with any number of focuses can be used.

〔Effect of the invention〕

As explained above, according to the present invention, by adding an identification signal to a command signal and providing a recognition means inside the DSP, a single command bus can be used to transmit signals from the CPU to each DSP while maintaining the simplicity of the transmission procedure. A parallel digital signal processing device capable of transmitting command signals can be provided.

Furthermore, according to the present invention, it is also possible to transmit instructions as serial signals, so a parallel digital signal processing device that can transmit instructions from a CPU to each DSP using an existing communication line such as a telephone line can be used. can be provided.

[BRIEF DESCRIPTION OF THE DRAWINGS] FIG. 1 is a block diagram of a parallel digital signal processing device according to an embodiment of the present invention, and FIG. 2 is a diagram showing an example of the bit configuration of a command signal in which an identification signal is added to the command signal. , Figure 3 is a circuit diagram of an identification signal recognition circuit that recognizes an identification signal added to a command signal sent in parallel, and Figure 4 is a circuit diagram of an identification signal recognition circuit that identifies an identification signal added to a command signal sent serially. FIG. 5 is a block diagram of an example of a conventional parallel digital signal processing device. 10...CPU (central processing unit), 12, ~12.
...DSP (digital signal processing device), 14...
Data bus, 16...Instruction bus 22.24.26...
・Register, 30... Decoder, 31... Instruction register, 2 ・
...AND gate.

Claims (1)

[Claims] A central processing unit and a plurality of digital signal processing processors are connected through a data bus and an instruction bus, and data is processed in parallel by the plurality of digital signal processing processors based on instructions from the central processing unit. In the parallel digital signal processing device, an identification means indicating which digital signal processing processor is to be operated is added to an instruction signal supplied from the central processing unit to the plurality of digital signal processing processors through the instruction bus, A parallel digital signal processing device, characterized in that a digital signal processor is provided with recognition means for recognizing the identification means.