JPS62107304A - Programmable controller - Google Patents

Abstract

PURPOSE:To constitute the titled controller so that a dummy input for a simulation can be switched automatically in accordance with an address of a peripheral equipment which has been registered in advance, by comparing and discriminating the addresses, when a CPU has executed a read-out operation of the address of its peripheral equipment, and sending out a discriminating signal to a switching element, when they are equal. CONSTITUTION:An address of a peripheral equipment for executing a dummy input is registered in advance in a registration address memory 7 for simulation. Also, with respect to an address of the peripheral equipment for a simulation, information of on and off is written in an image memory 4 for input. Subsequently, when a CPU 1 executes an operation for reading out the address of its peripheral equipment, an output from a registration address memory 7 for simulation which has been registered already, and the address of the peripheral equipment which has been designated by the CPU 1 are compared and discriminated by a comparing element 8, and when they are the same, a discriminating signal (called an equal signal) of its fact is outputted. This equal signal is inputted to a select input terminal S of a switching element 9, an in[put terminal A of the switching element 9 becomes effective, and said signal becomes an input data of the CPU 1 through an output terminal Y of the same switching element 9.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a programmable controller l, and more particularly to a programmable controller having a function of simulating human power from a peripheral device.

[Conventional technology]

FIG. 2 is a block circuit diagram of a programmable controller that performs conventional simulation functions.

In the figure, 1 is the central performance X device! ! (hereinafter abbreviated as + CPU), 2 is an OR logic element, 3 is a process input,
4 is input image memory, 5 is address bus, 6 is Qi') Ha, ;', 1? , Riru.

Next, the operation of the conventional programmable controller shown in FIG. 2 will be explained.

When the process input 3 shown in the figure is off, if the + CPU inputs the ON signal to the input image memory 4 via the rear address bus 5, -OR logic element 2. C via data bus 6
A simulated on signal is applied to the PUI. On the other hand, if the input image memory 4 is turned off, the same <OR logic element 2.
A simulated off signal is input to the CPUI via the data bus 6.

[Problem that the invention seeks to solve]

Conventional programmable controllers are configured as described above, so when process power 3 is on, C
There was a problem that simulated input could not be performed on the PUI.

This invention was made in order to solve the above-mentioned problems: 1) The simulated input for simulation can be done manually by automatically switching between inputs according to the addresses of peripheral devices registered in advance. The purpose is to obtain a programmable controller.

[Pause: Means for solving hidden points]

A programmable controller according to this invention.

A simulation registration address memo jJ in which addresses of peripheral devices to be simulated are registered in advance, and an output from this simulation registration address memory and C.
It is equipped with a comparison element for comparing and determining the address of the peripheral device designated by the PU, and a switching element for automatically switching between the process input and the manual image memory based on the determination signal from the comparison element. It is.

[Effect]

In the programmable controller of the present invention, the registration address memory for simulation.

The address of the peripheral device to be simulated input is registered in advance, and when the CPU performs an operation to read the address of the peripheral device, it is output from the already registered simulation registration address memory.

The address of the peripheral device designated by the CPU is compared with the address of the peripheral device using the fi element, and when they are the same, a 0 determination signal is sent to the switching element. Based on this discrimination signal, the switching element automatically switches between the process signal and the input image memory, and the CPU
As input data to.

〔Example〕

FIG. 1 is a block circuit diagram of a programmable controller that is an embodiment of the present invention, and the same or equivalent parts as the conventional programmable controller shown in FIG.
The same symbols are attached.

In the figure, 7 is a registration address memory for simulation in which addresses of peripheral devices to be simulated input are registered in advance, and 8 is a comparison of the output from this registration address memory 7 with the address of the peripheral IT designated by the CPU 9. The ratio 1-bit element 9 is a switching element for automatically switching between the process input and the input image memory based on the determination No. 13 from the comparison element-8.

In particular, I would like to invent about the operation of the programmable controller.

First, the address of the peripheral device to be simulated manually is registered in advance in the ff1fi address memory 7 for simulation. In addition, the image memory 4I for inputting on/off information to the address of the peripheral 1 to be simulated.
3.

Next, when the + CPUI performs an operation to read the address of the peripheral device, the output from the already registered simulation registration address memory 7 is read.

Compare element 8 with the address of the peripheral device specified by the CPUI.
If they are the same, a discrimination signal to that effect (equal signal) is output. This equal signal enters the select input terminal S of the switching element 9, and the input terminal A of the switching element 9 becomes valid.
It becomes the input data of the CPUI via the output terminal Y of the .

〔Effect of the invention〕

As described above, according to the present invention, the address of a peripheral device to be simulated input is registered in advance in the registration address memory for simulation, and when the CPU performs an operation to read the address of the peripheral device, They are compared and discriminated by the comparative element, and if they are equal, a discrimination signal is sent to the switching element, and the switching element automatically
Since the process input and the input image memory can be switched, the simulation input can be automatically switched in accordance with the pre-registered peripheral device address. Dechiru.

[Brief explanation of drawings]

FIG. 1 is a block circuit diagram of a programmable controller according to an embodiment of the present invention, and FIG. 2 is a block circuit diagram of a conventional programmable controller. In the figure, 1...CPU-3...process input. 4...Image memory for input, 5...Address bus. 6...Data bus, 7...Registered address memory for simulation, 8...11i12 elements, 9...
It is a switching element. In each figure, the same reference numerals indicate the same or equivalent parts. Dai J” person Masuo Oiwa Figure 1. 6:・2-7 bus

Claims (1)

[Claims] In a programmable controller that performs simulation by simulated input from a peripheral device, there is a registration address memory for simulation in which the address of the peripheral device to which simulated input is registered in advance, and an output from the registered address memory for simulation and the address specified by the central processing unit. a comparison element for comparing and determining whether or not the addresses of the peripheral device are equal, and when the output from the simulation registration address memory and the address of the peripheral device designated by the central processing unit are equal; A programmable controller comprising: a switching element for automatically switching between a process input and an input image memory based on a discrimination signal from the comparison element.