JPS60122449A - Input and output controller of address variable system - Google Patents

Input and output controller of address variable system

Info

Publication number
JPS60122449A
JPS60122449A JP22995383A JP22995383A JPS60122449A JP S60122449 A JPS60122449 A JP S60122449A JP 22995383 A JP22995383 A JP 22995383A JP 22995383 A JP22995383 A JP 22995383A JP S60122449 A JPS60122449 A JP S60122449A
Authority
JP
Japan
Prior art keywords
address
input
output
circuit
channel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP22995383A
Other languages
Japanese (ja)
Inventor
Michinobu Kimura
木村 道信
Tomizo Kimura
木村 富蔵
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP22995383A priority Critical patent/JPS60122449A/en
Publication of JPS60122449A publication Critical patent/JPS60122449A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10Program control for peripheral devices
    • G06F13/12Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/122Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware performs an I/O function other than control of data transfer

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)

Abstract

PURPOSE:To improve the performance of general-purpose by constituting the titled controller than an input/output controller address is set again optionally from a basic processing unit via an input/output interface to improve the working performance of the controller. CONSTITUTION:An input and output address value transmitted from a channel is transmitted to a comparator circuit 3 via a receiver circuit 1. On the other hand, either a specific address value or an optional address value received by an optional address value storage circuit 7 is selected and stored in an address register 5. Further, the comparator circuit 3 compares the input/output address from the channel with the value of a register 5 and only when they are coincident, a driver circuit 4 is started to respond to the channel. The change in the input/ output controller address by the basic processing unit is changed into an optional address storage circuit 7 via an input/output channel interface, then the circuit 6 is started and the content stored in the circuit 7 is transferred to the register 5.

Description

【発明の詳細な説明】 〔発明の技術分野〕 この発明は、アドレス可変方式の入出力制御装置、特に
入出力チャネル・インタフェースを介シて基本処理装置
に接続されることにより入出力制御装置の人出力アドレ
ス値を任意に設定できる入出力制御装置に関するもので
ある。
[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a variable address input/output control device, and particularly to an input/output control device connected to a basic processing unit via an input/output channel interface. This invention relates to an input/output control device that can arbitrarily set human output address values.

〔従来技術〕[Prior art]

従来の人出力制御装置として、第1図に示すアドレス固
定方式のものおよび第一図に示すアドレス不定方式のも
のがあった。図において、/はチャネル(図示しない)
から送られてきた入出力アドレス値を受け取るレシーバ
回路、コは固有アドレス値を設定する手段例えばROM
またはスイッチ類、3はレシーバ回路/および固有アド
レス値設定手段]へ接続されて上述した両アドレス値を
比較する回路、ダはこの比較回路3および固有アドレス
値設定手段2へ接続されてチャネルに応答するためのド
ライバ回路、3はl/シーバ回路/とドライバ回路ダの
間に挿入されてレシーバ回路lで受信した入出力アドレ
ス値を格納するアドレス・レジスタである。
2. Description of the Related Art Conventional human output control devices include a fixed address type shown in FIG. 1 and an unfixed address type shown in FIG. In the figure, / is a channel (not shown)
The receiver circuit receives the input/output address values sent from the ROM.
or switches, 3 is a receiver circuit/and a unique address value setting means] and is connected to a circuit for comparing both address values, and DA is connected to this comparison circuit 3 and unique address value setting means 2 to respond to the channel. A driver circuit 3 is inserted between the receiver circuit 1 and the driver circuit DA, and is an address register for storing input/output address values received by the receiver circuit 1.

次に第1図に示したアドレス固定方式の人出力制御装置
の動作について説明する。チャネルから送られてきた人
出力アドレス値すなわちアドレス情報はレシーバ回路/
に入り、その後比較回路3において固有アドレス値設定
手段−で予め設定されている固有アドレス値と比較され
る。両アドレス値が一致すると、比較回路3はドライバ
回路りを起動して固有アドレス値を出力させ、従って入
出力制御装置はチャネルに応答することになる。
Next, the operation of the fixed address type human output control device shown in FIG. 1 will be explained. The human output address value or address information sent from the channel is sent to the receiver circuit/
Thereafter, in the comparator circuit 3, it is compared with the unique address value set in advance by the unique address value setting means. When both address values match, the comparator circuit 3 activates the driver circuit to output a unique address value, so that the input/output controller responds to the channel.

次に第2図に示したアドレス不定方式の入出力制御装置
の動作について説明する。チャネルから送られてきた人
出力アドレス値はレシーバ回路/を経由してアドレス・
レジスタ5に格納されると共にドライバ回路yを起動し
て入出力制御装置を無条件にチャネルに応答させる、す
なわちけの入出力制御装置は全ての人出力アドレス値に
応答する。
Next, the operation of the address indefinite type input/output control device shown in FIG. 2 will be explained. The human output address value sent from the channel is sent to the address via the receiver circuit.
It is stored in register 5 and activates driver circuit y to make the I/O controller respond to the channel unconditionally, ie, the I/O controller responds to all human output address values.

従来方式の入出力制御装置は以上のように構成されてい
るので、アドレス固定方式の入出力アドレス値を変更す
る場合にはROMの交換またはスイッチの再設定等の作
業を必要とし、またアドレス不定方式の場合はチャネル
に接続できる入出力制御装置の数が/台//チャネルに
限られてしまうなどの欠点があった。
Since the conventional input/output control device is configured as described above, changing the input/output address value of the fixed address method requires work such as replacing the ROM or resetting the switch, and also causes the address to be undefined. This method has drawbacks such as the number of input/output control devices that can be connected to a channel is limited to /unit//channel.

〔発明の概要〕 この発明は上記のような従来のものの欠点を除(3) 去するためになされたもので、アドレス固定方式にアド
レス不定方式のアドレス・レジスタ機能を組込み、基本
処理装置より入出力チャネル・インタフェースな介して
入出力制御装置の人出力アドレス値を任意に再設定でき
るアドレス可変方式の入出力制御装置を提供することを
目的としている。
[Summary of the Invention] This invention was made in order to eliminate (3) the drawbacks of the conventional devices as described above, and it incorporates the address register function of the address indefinite method into the fixed address method, and allows input from the basic processing unit. It is an object of the present invention to provide a variable address type input/output control device that can arbitrarily reset the human output address value of the input/output control device via an output channel interface.

〔発明の実施例〕[Embodiments of the invention]

以下、この発明の一実施例を図について説明する。第3
図において、/、2は第1図におけるのと同様なそれぞ
れレシーバ回路、固有アドレス値設定手段、3はチャネ
ルから送られてきてレシーバ回路/で受け取った入出力
アドレス値と入出力制御装置の後述する固有アドレス値
または任意アドレス値とを比較する回路、夕はチャネル
に応答するためのドライバ回路、左は固有アドレス値ま
たは任意アドレス値を格納しておくアドレス・レジスタ
、6はこのアドレス・レジスタSへの再設定動作を制御
する論理回路、りは基本処理袋M(図示しない)からそ
のプログラムで入出力チャネル・インタフェース(図示
しない)を介して送られてきた任意のアドレス値を保持
する回路である。
An embodiment of the present invention will be described below with reference to the drawings. Third
In the figure, /, 2 are respective receiver circuits and unique address value setting means similar to those in FIG. 6 is a circuit that compares the unique address value or arbitrary address value, the driver circuit for responding to the channel, the left is an address register that stores the unique address value or arbitrary address value, and 6 is this address register S. The logic circuit that controls the resetting operation is a circuit that holds any address value sent from the basic processing bag M (not shown) via the input/output channel interface (not shown) in the program. be.

次に動作について説明する。第3図において、チャネル
より送られてきた入出力アドレス値はレシーバ回路/を
経由して比較回路3に送られる。
Next, the operation will be explained. In FIG. 3, the input/output address value sent from the channel is sent to the comparator circuit 3 via the receiver circuit.

一方アドレス・レジスタSKは、固有アドレス値設定手
段ぼによって設定された人出力制御装置に固有のアドレ
ス値または基本処理装置から入出力チャネル・インタフ
ェースを介して任意アドレス値保持回路りで受け取った
任意のアドレス値のどちらかが論理回路6によって選択
されて格納されている。比較回路3ではチャネルより送
られてきた人出力アドレスとアドレス・レジスタ!の値
とが比較され、一致したときのみドライバ回路りを起動
してチャネルに応答する。基本処理装置による入出力制
御装置アドレスの変更は、まず入出力チャネル・インタ
フェースを介して任意アドレス値保持回路りに変更した
いアドレス値を保持させた後、論理回路6を起動して任
意アドレス値保持回路7に保持されている内容をアドレ
ス・レジスタjに移すことにより、可能となる。
On the other hand, the address register SK contains an address value specific to the human output control device set by the specific address value setting means or an arbitrary address value received by the arbitrary address value holding circuit from the basic processing unit via the input/output channel interface. One of the address values is selected by the logic circuit 6 and stored. In comparison circuit 3, the human output address and address register sent from the channel! and only when they match, activates the driver circuitry to respond to the channel. To change the input/output control device address by the basic processing unit, first, the arbitrary address value holding circuit holds the address value to be changed via the input/output channel interface, and then the logic circuit 6 is activated to hold the arbitrary address value. This is made possible by moving the contents held in circuit 7 to address register j.

なお、上記実施例では人出力制御装置の場合について説
明したが、人出力制御装置のシミュレータやチャネル・
テスタであってもよく、上記実施例と同様かあるいはそ
れ以上の効果を奏する。
Note that although the above embodiment describes the case of a human output control device, it can also be applied to a simulator of a human output control device or a channel/output control device.
A tester may also be used, and the effect is similar to or better than that of the above embodiment.

〔発明の効果〕〔Effect of the invention〕

以上のように、この発明によれば人出力制御装置アドレ
スを基本処理装置から人出力チャネル・インタフェース
を介して任意に再設定可能とするように構成したので、
装置の作業性が改善され、汎用性が増すという効果があ
る。
As described above, according to the present invention, the human output control device address can be arbitrarily reset from the basic processing device via the human output channel interface.
This has the effect of improving the workability of the device and increasing its versatility.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図および第2図は従来方式の入出力制御装置のブロ
ック図、第3図はこの発明の一実施例を示すブロック図
である。 /・・レシーバ回路、コ・・固有アドレス値手段、3・
・比較回路、ダ・・ドライバ回路、!・・アドレス・レ
ジスタ、6・・論理回路、り・・任意アドレス値保持回
路。 なお、各図中、同一符号は同−又は相当部分を示す。
1 and 2 are block diagrams of a conventional input/output control device, and FIG. 3 is a block diagram showing an embodiment of the present invention. /...Receiver circuit, Co...Unique address value means, 3.
・Comparison circuit, driver circuit,! ...address register, 6..logic circuit, ri..arbitrary address value holding circuit. In each figure, the same reference numerals indicate the same or corresponding parts.

Claims (1)

【特許請求の範囲】[Claims] チャネルから送られてきた人出力アドレス値とアドレス
レジスタに格納されている入出力制御装置の固有のアド
レス値または任意のアドレス値とを比較する前記入出力
制御装置であって、前記任意のアドレス値が基本処理装
置から入出力チャネル・インタフェースを介して変更可
能とされることを特徴とするアドレス可変方式の入出力
制御装置。
The input/output control device compares a human output address value sent from a channel with a unique address value or an arbitrary address value of the input/output control device stored in an address register, the arbitrary address value 1. A variable address type input/output control device, characterized in that the address can be changed from a basic processing unit via an input/output channel interface.
JP22995383A 1983-12-07 1983-12-07 Input and output controller of address variable system Pending JPS60122449A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22995383A JPS60122449A (en) 1983-12-07 1983-12-07 Input and output controller of address variable system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22995383A JPS60122449A (en) 1983-12-07 1983-12-07 Input and output controller of address variable system

Publications (1)

Publication Number Publication Date
JPS60122449A true JPS60122449A (en) 1985-06-29

Family

ID=16900296

Family Applications (1)

Application Number Title Priority Date Filing Date
JP22995383A Pending JPS60122449A (en) 1983-12-07 1983-12-07 Input and output controller of address variable system

Country Status (1)

Country Link
JP (1) JPS60122449A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62126455A (en) * 1985-11-27 1987-06-08 Ascii Corp Input/output port
JPS62284450A (en) * 1986-06-02 1987-12-10 Ascii Corp I/o selecting device
JPS6324343A (en) * 1986-07-16 1988-02-01 Fujitsu Ltd I/o address decoding system

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62126455A (en) * 1985-11-27 1987-06-08 Ascii Corp Input/output port
JPS62284450A (en) * 1986-06-02 1987-12-10 Ascii Corp I/o selecting device
JPS6324343A (en) * 1986-07-16 1988-02-01 Fujitsu Ltd I/o address decoding system
JPH0562786B2 (en) * 1986-07-16 1993-09-09 Fujitsu Ltd

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