JPS62284450A - I/o selecting device - Google Patents

Abstract

PURPOSE:To easily control I/O addresses when the kinds of I/O devices are different each other by making a driver program corresponding to each of plural I/O devices and selecting the I/O device corresponding to an operating driver program. CONSTITUTION:A computer 10 commands a memory selecting means 20 to generates a driver program selecting signal to an output terminal 21, and simultaneously generates a memory reading timing signal to a terminal 13. Consequently, an output is generated from an AND circuit 32 and driver program 31 starts to operate and outputs an I/O request. When an I/O request is included in the program 31 the request is fetched by the computer 10 and corresponding I/O address decoders 33, 33a output address coincidence signals. Since the driver program selecting signal is latched by a latch 35, an output is generated from an AND circuit 36 and a printer 50 is driven through an I/O interface 34.

Description

[Detailed description of the invention] 3. Detailed description of the invention [Industrial application field] The present invention relates to an I/O selection device.

[Conventional technique m1 When connecting multiple I/Os (input/output devices) to one computer and selecting one I/O from them for access, conventionally the configuration shown in Fig. 2 is used. We are hiring.

In other words, as a plurality of Ilo's, the first printer 50, the second printer 50,
An I/O controller 40.40a is provided with printers 50a, . . . and selectively drives these I/Os.
,...... are provided.

The I/O controller 40 includes a ROM 41 storing a driver program, an AND circuit 42, a 1/O address decoder 43, and a 1/O interface 44. The driver program 41 is a program that drives the first printer 50, and the AND circuit 42
This is a circuit that ANDs the memory read timing signal from the computer/O and the drive program selection signal from the memory selection means 20.

! /O controller 40a is a driver program 41
a Left, AND circuit 42a and I/O address decoder 4
3a and an I/O interface 44a. The driver program 41a is the second printer 50
The AND circuit 42a is a circuit that ANDs the memory read timing signal from the computer/O and the drive program selection signal from the memory selection means 20.

I/O: 17 troller 40. Other than 40a (7) I/O
The O controller has the same configuration as above.

Note that the memory selection means 20 selects one driver program among the plurality of driver programs 41, 41a, . . . .

The I/O address decoder 43 decodes the I/O address sent via the I/O address line 12, and when the address matches the address specific to the I/O controller 40, it assigns m to it. It is designed to drive the first printer 50 that is regulated.

The I/O address decoder 43a decodes the I/O address sent via the I/O address line 12, and when the address matches the address specific to the I/O controller 40a, The second printer 5Qa connected thereto is driven.

By the way, there is a limit to the number of I/O addresses, and if you use all the I/O addresses within that limit, you will not be able to use any more I/O addresses.
There is a problem that /O cannot be extended.

Furthermore, since the I/O address needs to be different for each Ilo, there is a problem that the I/O controller cannot be shared.

Furthermore, even when using I/O within the above limits, I/O
There is a problem in that it is necessary to allocate a different address to each lo, and the address management is complicated.

[Object of the Invention] The present invention has been made by focusing on the problems of the conventional device described above.If the type of Ilo is the same, the same I/O controller can be used, and if the type of Ilo is different, the same I/O controller can be used. It is sometimes an object of the present invention to provide an I/O selection device that can facilitate the management of I/O addresses.

[Summary of the Invention] The present invention provides the following features in order to facilitate the management of I/O addresses and to make it possible to use a common I/O controller except for the I/O interface.
A plurality of driver programs for driving I/Os are provided, one of the above driver programs is made to correspond to each of the plurality of I/Os, and one of the above driver programs is set to the I/O corresponding to the currently operating driver program. This is something you can choose from.

[Example of actual rod of the invention] FIG. 1 is a block diagram showing one embodiment of the present invention.

The difference between the embodiment shown in FIG. 1 and the conventional example shown in FIG. 2 is that an I/O controller 30.30a is provided in place of the /O (input/output bag a) controller 40.40a. It is a point.

The I/O controller 30 includes a driver program 31, an AND circuit 32, an I/O address decoder 33,
It has an engineering/O interface 34, a latch 35, and an AND circuit 36.

Driver program 31. AND circuit 32, I/O address decoder 33. The I/O interfaces 34 each have a driver program 41 . ANDD
Road 42. This is similar to the L/O7 decoder 43 and I/O interface 44.

The latch 35 is used to turn on the driver program selection signal generated at the output terminal 21 of the memory selection means 20, and the AND circuit 36 is used to turn on the driver program selection signal generated at the output terminal 21 of the memory selection means 20.
3 and the driver program selection signal latched by the latch 35.

Similar to the above, the I/O controller 30a also has a latch 35a and an AND when compared with the I/O controller 40a.
A new circuit 36a is provided.

Furthermore, if only Ilo's of the same type are connected, their I/O addresses are the same. In other words, if the first printer 50 and the second printer 50a are the same, their I
The /O address is also the same.

In other words, the same I/O address is used when selecting the first printer 50 and when selecting the second printer 50a.
/O is output to the address line 12. Therefore, I
/O address decoder 33 and I/O address decoder 3
3a is the same, driver programs 31 and 3
1a is the same, and the I/O controllers 30 and 30a
are the same.

Next, the operation of the above embodiment will be explained.

First, the case of selecting the first printer 50 will be described.

In this case, the computer/O instructs the memory selection means 20 to generate a driver program selection signal at its output terminal 21 (terminal corresponding to the first printer 50). At the same time, a memory read timing signal is generated at the terminal 13. As a result, the AND circuit 32 outputs an output, the driver program 31 starts operating, and the driver program 31 issues an I/O request.

In this way, if there is an I/O7 request in the driver program 31, the computer 11 receives the request, and the corresponding I/O address decoder 33, 33a outputs an address match signal. On the other hand, since the latch 35 latches the driver program selection signal, the AND circuit 36 outputs an output, and the printer 50 is driven via the I/O interface 34.

By the way, the I/O address decoder 33a outputs an address match signal, but since the latch 34a does not latch the driver program selection signal, the AND circuit 36a does not output and the printer 50a does not drive.
This means that only the first printer 50 has been selected.

Next, the case of selecting the I/O controller 30a will be explained.

In this case, the computer/O instructs the memory selection means 20 to generate a driver program selection signal at its output terminal 22 (terminal corresponding to the second printer 50a). At the same time, a memory read timing signal is generated at the terminal 13. This allows AND
The circuit 32a outputs an output, the driver program 31a starts operating, the driver program 3ta issues an l-/O request, and the computer 11 receives the request.
The corresponding I/O address decoder 33.33a outputs an address match signal. On the other hand, since the latch 35a latches the driver program selection signal, the AN
The D circuits 3 and 6a output, and the I/O interface 34a
The printer 50a is then driven.

However, since the latch 34 does not latch the driver program selection signal, the AND circuit 3
6 does not output, and the printer 50 does not drive. Therefore, only the first printer 50a is selected.

In the above case, the address sent to I/O address line 12 is the same address as when selecting first printer 50. This means that the I/O controller 30.
The same can be said for I/O controllers other than 30a. Therefore, no matter which I/O controller you choose, as long as the connected Ilo is the same, the I/O
The addresses are the same. Therefore, management of I/O addresses is very easy.

Also, since the I/O addresses are the same, ■/O address decoders 33, 33a, .
I/O controller 30.30a...
...The whole thing can be made common. Furthermore, there is no limit to the number of I/O addresses.

For example, the above embodiment deals with a case where only Ilo of the same type is likely to be connected, but it is also possible to connect multiple types of I/O. In this case, the computer /O
As the I/O addresses sent from the address line 12 to the I/O address line 12, seven addresses corresponding to the number of types (for example, two addresses if there are two types) are output. In this case,
Generally, the number of I/O addresses is smaller than the total number of connected Ilo's, so address management becomes easier.

Various methods of expanding the memory in the memory selection means 20 are known, and the present invention may use any of them.

Further, in the above embodiment, the memory selection means 20 is provided outside the I/O controller, but the memory selection means 20 is omitted and a memory address register is provided inside the I/O controller 30. It's okay.

[Effect of the invention] According to the present invention, if the type of work/O is the same, the same I
The /O controller can be used, and when the types of Ilo are different, it has the effect that the management of the /O address can be facilitated.

[Brief explanation of drawings]

The gSt diagram is a block diagram showing one embodiment of the present invention. Figure 2 shows a conventional I/O selection device.
This is a diagram. 20...Memory selection means, 30, 30a'' I/O: 1 controller. 31.31a...Driver program, 33.33a
...I/O address decoder. 35... Latch, 50... First printer, 50a... Second printer.

Claims (1)

[Claims] A plurality of driver programs for driving I/Os are provided, one driver program is made to correspond to each of the plurality of I/Os, and among the driver programs, the I/O corresponding to the currently operating driver program is set. An I/O selection device characterized by making a selection.