JPH0739086Y2 - FDD control circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial field of application) The present invention relates to a control circuit for a floppy disk drive (FDD).

(Prior art) Multiple floppy disk drive units (hereinafter referred to as FD
The FDD control element generally has a limit in the number of units that can be controlled, for example, μPD765 has a limit of 4 units.

(Problems to be solved by the invention) In the FDD control circuit using the FDD control element as described above, when it is attempted to control the number of units exceeding the limit of the number of units, the FDD control element is required. It was necessary to add only the number or use an external unit selection circuit separately. When an external unit selection circuit is used, a program is added for each addition to selectively use the unit selection signal output from the external selection circuit and the unit selection signal output from the FDD control element. Otherwise, there was a problem that the unit selection function of the FDD control element would be impaired.

The present invention adds a program for selecting the FDD unit to the host in advance without adding a special unit selection circuit, so that the number of units exceeding the number of units that can be selected by the FDD control element is exceeded. It is an object of the present invention to provide a circuit capable of controlling each unit.

(Means for Solving Problems) In order to solve the above problems, the present invention provides an FDD in which the number of controllable units is limited to a predetermined number and the predetermined number of FDD units can be individually sought. Equipped with control element, F
In the FDD control circuit for computer-controlling the DD unit, the unit selection code for selectively designating each control target unit having a number of bits exceeding the predetermined number and having a number exceeding the predetermined number is the address of the predetermined number. A unit selection signal storage unit, which is pre-written corresponding to each of the units, enables the unit selection code to be appropriately rewritten and read, and provides the read unit selection code to the FDD unit side, and the control. Each time a unit control command for designating to select a target unit is sent from the host, an address corresponding to the unit control command is specified in the unit selection signal storage unit to control the reading of the unit selection code. Read control means for

(Operation) In the unit selection signal storage unit, unit selection for selectively designating each control target unit in a number exceeding the predetermined number in correspondence with each address consisting of a predetermined number controllable by the FDD control element The code for use is written in advance with a predetermined bit length exceeding the predetermined number, and is read by the read control means every time a unit control command is sent from the host, to the unit selection signal storage section. An address corresponding to the unit control command is designated, the unit selection code is read from the unit selection signal storage section, and the read code is
It is given to the FDD unit side. When performing selection control by combining with a new FDD unit, rewrite the unit selection code in the unit selection signal storage unit to correspond to the selection designation of the new FDD unit for each address. Then, the unit selection code is similarly read and given to the FDD unit side.

(Embodiment) FIG. 1 shows an embodiment of the FDD control circuit of the present invention. Here, four 8-inch units and four five-inch units are used.
-1 out of 8 FDD units with 1/4 inch unit,
An example is shown in which selection control is possible for any four units.

In the figure, CPU is the central processing unit of the computer, FDD
Is a FDD control element (hereinafter referred to as a control element), and RAM is a 2-port random access memory (hereinafter referred to as a memory) capable of simultaneously writing and reading data. The FDD unit that is selectively controlled is indicated by the reference numeral FDD in the same figure.

The memory RAM is the unit selection signal storage of the present invention,
A unit selection code for each FDD unit (not shown) to be selected is stored in advance. In this storage, the addresses are sequentially specified through the address line L1 and the write line L2 by the control of the central processing unit CPU.
A write command is received via the
It receives the unit selection code via L3 and takes in it. When changing the previous selection target, the previous stored contents are rewritten in the same manner.

FIG. 2 is a diagram showing an example of data stored in the memory RAM. In the figure, the memory RAM has four areas, and each area has an address code A2A1 “00” through the address line L1.
Specified by "11". Bits D4, D3, D2, D1 and D0 indicate the stored unit selection codes, and the bit length exceeds the number of units that can be simultaneously controlled by the control element FDC, which is 1 in this case. It consists of 5 bits, and the data "0" of the most significant bit D4 specifies the selection of 5-1 / 4 inch unit, and "1" specifies the selection of 8 inch unit. Then, the data “1” of each of the bits D3, D2, D1, D0 is F
Specifies the selection of each corresponding unit among the 4th to 1st DD. Therefore, this figure consists of a total of 8 units of 4 units consisting of the 4th to 1st of the 5-1 / 4 inch FDD and 4 units consisting of the 4th to the 1st of the 8 inch FDD. It is shown that four of the FDD units are appropriately designated as control targets in advance and the four FDD units of the control targets are selectively selectable.

Specifically, in FIG. 2, the first 5-1 / 4 inch FDD unit, the second 5-1 / 4 inch FDD unit, the first 8 inch FDD unit, and the third 8 inch FDD unit are shown. , Address code “00”, “01”, “10”, “1” respectively
"1" indicates that the selection can be specified.

In the figure, when changing the combination of four FDD units, the unit selection code of the memory RAM is rewritten in the same manner as the above storage operation.

In this case, the control element FDC is composed of an LSI generally known for each device μPD765, and receives the unit control command transmitted from the central processing unit CPU via a control line (not shown) and transmits the unit control command. For each unit, through the unit selection signal line L4, specify the read address corresponding to the unit control command to the memory RAM, and read each unit selection code D4 to D0 from the output line L5,
A control signal for the FDD unit is output from the unit control line L6 to control the FDD unit by the unit selection codes D4 to D0. In this way, the device μPD765 has four FDDs.
It outputs each address for selecting a unit and enables control of the unit.

In the above configuration, it is assumed that the code shown in FIG. 2 is stored in the memory RAM. Depending on the program from the central processing unit CPU, for example, the first FDD of 8 inches
When selecting and controlling a unit, the control element FDC receives the unit control command from the central processing unit CPU via a control line (not shown), and the unit concerned to the memory RAM via the unit selection signal line L4. Specify the read address “10” corresponding to the control command. As a result, the output line L5
The unit selection code "10001" is read from. Second
According to the codes shown in the figure, the first 8-inch FDD unit is selected, and the FDD unit is controlled via the unit control line L6. Thereafter, the addresses are sequentially changed and controlled in the same manner.
When controlling a control target unit different from that shown in FIG. 2, the memory RAM is rewritten in advance by a unit selection code which selectively designates a new control target with the above code length using the above address. Being
Controlled similarly.

(Effect of the Invention) As described above, according to the present invention, once the unit selection code is set in this control circuit prior to the control of the FDD unit, the above-mentioned setting is performed until the combination of the FDD unit is changed. The unit selection code is FD.
Since the D control element is set up to a predetermined number that can be controlled, each FDD by computer is set.
The control is relatively simple, without increasing the code involved in unit selection and control. The program for changing the combination of the units is temporarily operated during the setting and can be separated from the control of the normal unit, so that it can be added relatively easily.

[Brief description of drawings]

FIG. 1 is a block diagram of an FDD control circuit showing an embodiment of the present invention, and FIG. 2 is an example of data stored in the memory RAM shown in FIG. CPU: Central processing unit FDC: FDD control element RAM: Random access memory (unit selection signal memory)

Claims (1)

[Scope of utility model registration request] 1. An FDD control circuit for controlling a computer by controlling an FDD unit, the number of controllable units being limited to a predetermined number, and comprising an FDD control element capable of individually seeking the predetermined number of FDD units. A unit selection code having a number of bits exceeding the number and selectively designating each of the control target units exceeding the predetermined number is written in advance corresponding to each of the predetermined number of addresses, and the unit selection is performed. A unit selection signal storage unit that makes it possible to appropriately rewrite and read out the unit code and gives the read unit selection code to the FDD unit side, and a unit control command for designating to select the unit to be controlled. Each time a message is sent from the host, a unit corresponding to the unit control command is designated in the unit selection signal storage unit to specify the unit. FDD control circuit and a read control means, it characterized that control the reading of 択用 code.