JPH10177786A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To control a switch corresponding to a memory block by software by storing constitution information of a memory block corresponding to a memory address, while storing memory refresh control information, storing a memory block of refresh start/stop, calculating a memory block to be processed, and writing it in an I/O port. SOLUTION: A file in which memory block information is stored is read from an outer memory device 2, and set to a memory block information storing section 3. To record memory block information in the outer memory device 2 is to cope with that correspondence between an address range of a memory and a number of a memory block is different depending on a used system. Thereby, a memory block control section 1 can receive a memory refresh control command from a host device.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory refresh control device and method, and more particularly, to a power saving device, a random access memory is divided into a plurality of memory blocks, and only a memory block corresponding to a memory address from a host device is stored. And a memory refresh control device for turning on the memory.

[0002]

2. Description of the Related Art Conventionally, in a system mainly using a dynamic random access memory (hereinafter, referred to as a D-RAM), an increase in power consumption due to an increase in memory capacity has been a problem. Therefore, the D-RAM is divided into a plurality of memory blocks, and a switch for turning on / off a refresh signal input in units of memory blocks is provided to detect a change in each signal line of the address bus and control the corresponding switch. A memory refresh control device and method have been proposed.

That is, as this type of memory refresh control device, there is one described in, for example, JP-A-63-37893. Here, a switch for turning on / off a refresh signal input to each memory block is provided corresponding to each of the divided memory blocks, and is controlled by decoding an address signal line.

[0004]

However, the first problem here is that the detection of a memory bank that does not require refreshing has not been clarified at all. That is, regarding access to the memory, software such as an OS that manages the use state of the memory is required, but nothing is disclosed about this point.

[0005] The second problem is that the device cannot be miniaturized because a complicated logic circuit is required. This is because a circuit for decoding a signal line of an address for accessing the memory is required.

The present invention has been made based on the above circumstances, and an object of the present invention is to deal with a memory block by monitoring the use status of a memory block that is secured or released by a program. An object of the present invention is to provide a memo refresh control device and method for controlling and refreshing a switch from software.

Another object of the present invention is to provide a memory refresh control device capable of controlling on / off of a refresh signal of a memory block without requiring a complicated logic circuit.

[0008]

Therefore, in the present invention,
A memory refresh control device comprising: a random access memory divided into a plurality of memory blocks; and a switch corresponding to each of these memory blocks for turning on / off a refresh signal input to each memory block. Storage means for storing configuration information corresponding to a memory address, start / stop of refresh of the memory block from a higher-level device, and a memory including a range of memory addresses for starting / stopping the refresh A second storage unit for storing refresh control information, a third storage unit for storing a memory block targeted for the start / stop of the refresh, and a start / end of the refresh based on the memory refresh control information Calculate the target memory block Means for generating a number of a memory block, recording the number in the third storage means, and writing this information to an I / O port for controlling a refresh signal; The switch corresponding to the memory block is controlled so that only the refresh signal is turned on.

According to the present invention, the random access memory is divided into a plurality of memory blocks, and each of the selected memory blocks is turned on / off by a refresh signal from a higher-level device corresponding to each of the memory blocks. In the refresh control method, a corresponding memory block is selected from information of “start address” and “end address” by an instruction from a higher-level device based on a memory block number corresponding to a previously stored memory address range. This is stored separately, and the refresh signal of the memory block is turned on / off for the selected memory block.

In this case, information of "start address" and "end address" is stored by an instruction from a higher-level device, and the information of "refresh start / stop" is searched based on the number of the memory block. Originally, when the refresh is started, the number of the corresponding memory block is stored, and when the refresh is stopped, the number of the corresponding memory block can be deleted.

Therefore, the memory address to be refreshed is determined by converting the memory address secured or released by the program into the number of the corresponding memory block, and the memory block to be refreshed is determined according to the memory block number. Because it will control the / O port,
Regarding memory access, the use state of the memory can be managed by software, and a complicated logic circuit unlike the related art is not required.

[0012]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a configuration diagram showing an embodiment of the present invention. An external storage device 2 such as a hard disk, and a plurality of divided memory blocks corresponding to memory addresses recorded in the external storage device (the whole is shown by a memory group 7) ), A memory refresh control information storage unit 4, a memory refresh block storage unit 5, and a refresh control command from a host device. A memory block controller 1 for controlling the port 6;
And a switch group 8 for turning on / off the refresh of the memory block from the port 6.

As shown in FIG. 2, the memory block information storage unit 3 stores memory blocks (71 to 7) corresponding to the range of the memory addresses stored in the external storage device 2 on a one-to-one basis.
n) is stored. For example, an address range of 0 M to 2 M bytes is stored in the form of a memory block number “1”. Here, since the relationship between the range of the memory address and the memory block differs depending on the system to be used, the correspondence information is recorded in the external storage device 2 in advance.

The memory refresh control information storage unit 4
As shown in FIG. 3, refresh start / stop information included in a refresh control command from a higher-level device, and
A storage unit (41-43) for storing the start address and the end address is provided. Note that the refresh start / stop storage area is set so that when the content is "1", the refresh is started, and when the content is "0", the refresh is stopped.

The memory refresh block storage unit 5
As shown in FIG. 4, the number of the memory block for which the refresh signal is valid is stored. The storage method here is that the block number of the start of the refresh is stored in the storage area 51.
The block number of the end of the refresh is stored in the storage area 52.
And how to store them. The block number to be stored is calculated based on the information in the memory refresh control information storage unit 4 and referring to the correspondence table in the memory block information storage unit 3.

The I / O port 6 has a function of turning on / off each switch (81 to 8n) of the switch group 8 in units of bits in response to an instruction from the memory block control unit 1 (configuration of a register or the like). , Switch 81 is Bit: 0
The switch 82 corresponds to Bit: (n-1), and the switch 82 corresponds to Bit: (n-1). Each switch (81 to 8n) of the switch group 8
And each memory block (71-7n) of the memory group 7 is 1
One to one.

When the value to be written to (the register of) the I / O port is "1", the switches of the corresponding switch group 8 are turned on, and the refresh signal to the memory block of the corresponding memory group 7 is output. Becomes effective. Conversely, I
When the value to be written to (the register of) the / O port is “0”, the switches of the corresponding switch group 8 are turned off, and the refresh signal to the memory block of the corresponding memory group 7 becomes invalid.

Next, a control method according to an embodiment of the present invention will be described with reference to FIGS. First, when the memory block control unit 1 is started, "unused code" is set in all of the memory refresh block storage units 5 (step 101). Further, by writing "0" to all the bits of the I / O port 6, the refresh signal is prevented from being input to the memory blocks (71 to 7m) (step 102).

Next, the file storing the memory block information is read from the external storage device 2 and set in the memory block information storage unit 3 (step 103). In addition,
The reason for recording the memory block information in the external storage device is to cope with the fact that the correspondence between the address range of the memory and the number of the memory block differs depending on the system used as described above. Through the above processing, the memory block control unit 1 can receive a memory refresh control command from a higher-level device (not shown) (step 1).
04).

When the memory block control unit 1 receives a memory refresh control command from a host device, it extracts the information of "refresh start / stop", "start address" and "end address" in the command, and executes memory refresh. Storage areas 41, 42, 43 in control information storage unit 4
Are sequentially set (step 105).

Next, the memory block controller 1 determines whether the memory refresh control command from the host device is a command for instructing start or a command for instructing stop (step 106). When the memory refresh control command is a command for instructing start, the memory refresh control information storage unit 4
Of the memory block information storage unit 3
Of the memory address range (311 to 31n) in the memory block, and searches for the corresponding memory block number (32
1 to 32n) is set in the storage area (corresponding one of 511 to 51m) of the memory block at the start of refresh in the memory refresh block storage unit 5.

Similarly, the end address 43 is searched for any one of the memory address ranges (311 to 31n), and the corresponding memory block number (corresponding to the farmland 321 to 32n) is determined as the memory block at the end of the memory refresh (The corresponding one of 521 to 52m) (step 107).

The setting position is determined by the storage area (511-111) of the memory block at the start / end of the refresh.
51n / 521 to 52n), a check is made from the storage area of 511/521 to find the position where an unused code is first detected.

Next, in the case where the memory refresh control instruction is an instruction to stop, the start address 42 and the end address 43 in the memory refresh control information storage unit 4 are stored in the memory block information storage unit 3 as in the case of the start. Of the memory address range (311 to 31n) within the memory block, the corresponding memory block number (321 to 31n) is searched.
2n), the storage area of the memory block at the start of refresh in the memory refresh block storage unit 5 (the corresponding one of 511 to 51m), and
Storage area of memory block after refresh (521 to 521)
52m), and the storage area of the number of the matching block is changed to an unused code (step 108).

Next, a combination of each memory block of the refresh start / end of the memory refresh block storage unit 5 is taken out, converted into a bit string, and
(Step 109).

When the system is turned on, the memory address controller performs an access control output to the memory group 7 in the usual manner by CPU address request information and a refresh timing signal from the refresh controller. Further, the multiplexer outputs an MPX signal, and the multiplexer switches the column address and the row address of the address signal based on the MPX signal.

As described above, the processing from step 104 to step 109 is repeated until the system stops. Thus, in the present invention, by obtaining information on the use status of the memory from the host device, the memory block corresponding to the memory address is calculated, and the switch is turned on or off based on this memory block. In other words, the refresh signal is input only to the memory blocks that need to be refreshed.

[0028]

Next, a specific example of the embodiment of the present invention will be described with reference to a combination device in which the maximum memory capacity that can be mounted is 16 MB and the content of the memory block information storage unit 3 is as shown in FIG. The operation will be described.

In this embodiment, 0 megabytes (MB) to
The memory range of 2 MB-1 byte corresponds to the memory block number 1 and the memory range of 2 MB to 4 MB-1 byte corresponds to the memory block number 2 and thereafter.
The memory range of 14 MB to 16 M-1 bytes corresponds to the memory block number 8.

In this apparatus, when an instruction including the memory refresh control information as shown in FIG. 7 is received from the host apparatus (step 104), the information of the refresh start / stop (corresponding to the above-mentioned reference numeral 41) is "1". Because
It can be seen that the instruction is to start refreshing (step 106). Next, as shown in FIG. 6, at the start address “1 Mbyte”, the number of the memory block is “1”. In addition, the end address
In the case of "3 Mbytes", similarly, as is apparent from FIG.
It can be seen that the number of the memory block is “2”. Then, the content of the memory refresh block storage unit 5 is as shown in FIG. 8 (step 107).

Next, for example, in a combination as shown in FIG. 8, data is written to an I / O port. When the refresh start / end is a combination of “1” and “2”, the Bit is “1”. In the area where the unused code is set, this is ignored. When the above processing result is represented by a Bit string, it becomes "11", and when the Bit is "2" to "n-1", it becomes 0, and this value is written to the I / O port 6 (step 109).
By the above processing, the memory blocks 1 and 2 are targets for starting the refresh signal as the memory blocks requiring the refresh.

In the case where the contents of the memory refresh block storage unit 5 are as shown in FIG. 9 and a refresh stop instruction is received, as shown in FIG. It is converted into the number of the memory block by the search method described. Conversion Result "
3 "and" 4 ", and in this combination, the storage area of the memory block at the start / end of the refresh is searched and changed to the unused code" 0 ".
The contents shown in FIG.

Next, in the combination shown in FIG.
Assuming that data is written to the I / O port, if the refresh start / end combination is “1” and “2”, Bits: 0 and 1 become “1”, and “2” and “2”
In the combination of No. 2 ", Bit: 1 becomes" 1 "and"
The combination of No. 4 "and No. 4" indicates that Bit: 3 is "1".
Becomes The area where the unused code is set is ignored.

When the above processing result is represented by a Bit column, "1"
011 "and write this value to the I / O port 6 (step 109). With the above processing, although the memory block 3 is in the middle of the memory, refresh is not required, and the refresh signal can be stopped.

[0035]

The present invention has been described in detail above. Since the on / off of the refresh signal can be controlled in memory block units by managing the range of the memory address by the memory block number, the random access memory can be controlled. Of the memory can be suppressed to a necessary minimum, and the heat generated from the memory can also be suppressed. In addition, control can be performed even when a memory access occurs at random and refresh of a memory block in the middle becomes unnecessary. Further, unlike the related art, a complicated circuit for decoding an address signal line for accessing a memory is not required, so that the circuit can be downsized.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a diagram illustrating a configuration of a memory block information storage unit in FIG. 1;

FIG. 3 is a diagram illustrating a configuration of a memory refresh control information storage unit in FIG. 1;

FIG. 4 is a diagram illustrating a configuration of a memory refresh block storage unit in FIG. 1;

FIG. 5 is a diagram illustrating a processing procedure of a memory block control unit in FIG. 1;

FIG. 6 is a diagram showing a configuration of a memory block information storage unit showing a specific example of the present invention.

FIG. 7 is a diagram showing a case where the refresh start / stop in the memory refresh control information storage unit is set to “1”.

FIG. 8 is a diagram showing a configuration of a memory refresh block storage unit.

FIG. 9 is a diagram showing a configuration of a memory refresh block storage unit showing another specific example of the present invention.

FIG. 10 is a diagram illustrating a case where the start / stop of the refresh is set to “0” in the memory refresh control information storage unit.

FIG. 11 is a diagram showing a configuration of a memory refresh block storage unit as a result.

[Explanation of symbols]

 Reference Signs List 1 memory block control unit 2 external storage device 3 memory block information storage unit 4 memory refresh control information storage unit 5 memory refresh block storage unit 6 I / O port 7 memory group 8 refresh signal on / off switch group 71,... 7n memory Block 81, 8n switch

Claims (3)

[Claims] 1. A memory refresh control device comprising: a random access memory divided into a plurality of memory blocks; and a switch for turning on / off a refresh signal input to each memory block corresponding to each of the memory blocks. A first storage unit for storing configuration information of the memory block corresponding to a memory address; a start / stop of a refresh of the memory block from a higher-level device; and a memory address for starting / stopping the refresh. A second storage unit that stores memory refresh control information including a range of: a third storage unit that stores a memory block targeted for start / end of the refresh; and Memory block for which refresh starts / ends Means for calculating a memory block number, generating the number of the memory block, recording the number in the third storage means, and writing this information to an I / O port for controlling a refresh signal. A memory refresh control device, wherein a switch corresponding to a memory block is controlled so that a refresh signal is turned on only for a necessary memory block. 2. A memory refresh control method in which a random access memory is divided into a plurality of memory blocks, and corresponding to each of the memory blocks, a selected memory block is turned on / off by a refresh signal from a host device. Based on the memory block number corresponding to the previously stored memory address range, the corresponding memory block is selected from the information of “start address” and “end address” according to the instruction from the host device, and this is separately stored. A memory refresh control method characterized by turning on / off a refresh signal of the memory block for the memory block. 3. The information of "start address" and "end address" is stored by an instruction from a higher-level device, and is searched based on the number of the memory block, and the information of "refresh start / stop" is obtained. In the case of a refresh start,
3. The memory refresh control method according to claim 2, wherein the number of the corresponding memory block is stored, and when refreshing is stopped, the number of the corresponding memory block is deleted.