JPH10207825A - Data transfer device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To attain high speed data transfer by simultaneously executing data reading from a transferring source and data writing in a transferred destination between memories in different memory devices. SOLUTION: The data transfer device is provided with memory devices 1, 2, a direct memory access(DMA) device 3 and a data transfer control device 4. The memory devices 1, 2 include memories having the same memory space and same physical addresses. Only when 'H' signals are inputted from the control device 4 to chip select signal lines 13, 17, the memory devices 1, 2 permit reading from the device 4 when the 'H' signals are inputted from the device 4 to reading permission signal lines 14, 18 and inhibit reading when 'L' signals are inputted. Thus the data transfer device can simultaneously execute data reading from the transferring source and data writing in the transferred destination between the memories in the different memory devices 1, 2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a data transfer device.

[0002]

2. Description of the Related Art In recent years, when performing efficient data transfer, a DMA that performs data transfer by hardware without using a CPU has been used, and there is a demand for speeding up of a data transfer device using the DMA.

[0003] A conventional data transfer device and a memory-memory data transfer method will be described below. FIG. 7 shows a configuration of a conventional data transfer device. The conventional data transfer device has a memory device 69 and a DMA device 70.
The memory device 69 and the DMA device 70 are connected by a data signal line 72, an address signal line 71, a read permission signal line 73, and a write permission signal line 74.
The memory device 69 permits reading when "H" is input from the DMA device 70 to the read permission signal line 73, and prohibits reading when "L" is input thereto. Similarly, the memory device 69 permits writing when "H" is input to the write enable signal line 74 from the DMA device 70, and inhibits writing when "L" is input here.

The data transfer system of the conventional data transfer device configured as described above will be described below. FIG. 8 shows a timing chart of a conventional one-to-one memory-memory data transfer method. First,
To read the data of the data transfer source, the DMA device 70
Outputs the address of the transfer source to the address signal line 71, outputs “H” to the read permission signal line 73, and outputs “L” to the write permission signal line 74. Upon receiving these signals, the memory device 69 outputs transfer source data to the data signal line 72.

Next, to write data to the transfer destination,
The DMA device 70 outputs the address of the transfer destination to the address signal line 71, outputs “H” to the write enable signal line 74, and outputs “L” to the read enable signal line 73.

[0006] Upon receiving these signals, the memory device 69
The data on the data line 72 is written to the transfer destination. As described above, in the conventional one-to-one memory-memory data transfer method, a total of two cycles are required, one cycle for reading the source data and one cycle for writing to the destination.

FIG. 9 is a timing chart of a conventional one-to-many memory-to-memory data transfer system. In this case, as in the one-to-one memory-to-memory data transfer method, first, the transfer source data is read. Next, in order to write data to each transfer destination, the DMA device 70
Outputs the address of each transfer destination to the address signal line 71 for each cycle, outputs "H" to the write enable signal line 74, and outputs "L" to the read enable signal line 73.

[0008] Upon receiving these signals, the memory device 69
The data on the data signal line 72 is written to each transfer destination. As described above, in the conventional one-to-many memory-memory data transfer method, assuming that the number of transfer destinations is N, the total of N + 1 cycles is one cycle for reading source data and N cycles for writing to each destination. Requires a cycle.

[0009]

However, in the above conventional configuration, the time required for data transfer is the sum of the time required for reading data from the transfer source and the time required for writing data to the transfer destination. It has a disadvantage that it takes at least two cycles, and the transfer time becomes longer as the number of destinations increases.

An object of the present invention is to solve the above-mentioned conventional problems and to provide a data transfer device for performing high-speed data transfer.

[0011]

SUMMARY OF THE INVENTION In order to solve this object, a data transfer apparatus according to the present invention simultaneously reads data from a transfer source and writes data to a transfer destination between memories between different memory devices. It is something to do.

According to this, the data transfer between different memory devices can be performed at high speed by simultaneously performing the data read and the data write.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION
A device, a plurality of memory devices, comprising a data transfer control device for controlling the data read and data write to the memory device, the data transfer control device, between memories between different memory devices, It is configured to simultaneously read data from a transfer source and write data to a transfer destination.

[0014] According to this, the data transfer control device simultaneously performs the reading of the data of the transfer source and the writing of the data to the transfer destination between the memories between the different memory devices, whereby the data transfer between the different memory devices is performed. Data transfer can be performed at high speed. According to a second aspect of the present invention, different memory devices each include a memory having the same physical address, and the data transfer control device outputs a valid address to the memory device, and then outputs a chip select signal and data to the source memory. It is configured to output a read permission signal and output a chip select signal and a data write permission signal to a transfer destination memory.

According to this, the chip select signal, the data read permission signal, and the data write permission signal from the data transfer control device can be output for each memory device, and the data read and data write can be performed simultaneously. One-to-one or one-to-many data transfer between memories having the same physical address between different memory devices can be performed at high speed.

According to a third aspect of the present invention, the data transfer control device divides the memory by using the upper bits of the memory address as selector bits and the remaining bits as effective address bits, and Means for connecting a data signal line of an effective address bit length to each of the memories, and means for simultaneously reading data from a transfer source and writing data to a transfer destination between memories having the same effective address bits. Is what it is.

According to this, it is possible to select a memory device to which data is to be transferred and to set a memory having the same physical address between these memory devices, and to set the same physical address between different memory devices. Memory having
One-to-one or one-to-many data transfer between memories can be performed at high speed.

The present invention according to claim 4 is configured to perform one-to-one memory-to-memory data transfer between different memory devices. The present invention according to claim 5 is a method for transferring one memory device to a plurality of other memory devices.
It is configured to perform multi-memory data transfer between memories.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows a data transfer device according to a first embodiment of the present invention. In FIG. 1, 1 and 2 are memory devices, 3 is a DMA device, 4 is a data transfer control device, and 5 is a data signal line. 6 and 8 are the memory devices 1 and 2 of the DMA device 3.
, Data read request signal lines 7 and 9 are DM
Data write request signal lines for the memory device 1 and the memory device 2 of the A device 3
This is an address signal line for the entire memory area from another device such as a PU to the data transfer control device 4. 11 and 12
Are data read request signal lines and data write request signal lines for the entire memory area from other devices such as the DMA device 3 and the CPU to the data transfer control device 4.
13 is a chip select signal line for the memory device 1 of the data control device 4, 14 is a data read enable signal line for the memory device 1, 15 is a data write enable signal line for the memory device 1, and 16 is the memory device 1 of the data control device 4. And address signal lines for the memory device 2, 1
7 is a chip select signal line for the memory device 2 of the data control device 4, 18 is a data read enable signal line for the memory device 2, and 19 is a data write enable signal line for the memory device 2.

The memory device 1 and the memory device 2 of the data transfer device of the present embodiment have the same memory space, and memories having the same physical address are present. Also,
If the most significant bit of the address signal line 10 designating the entire memory area is "1", the memory of the memory device 1 indicated by the address excluding the most significant bit of the address signal line 10 is accessed, and "0" In the case, the memory device 2 indicated by the address excluding the most significant bit of the address signal line 10
To access memory.

FIG. 2 is a more detailed block diagram of the data transfer control device 4. In FIG. 2, reference numeral 20 denotes the most significant bit of the address signal line 10 for specifying the entire memory area, 21 denotes the lower bit address of the address signal line 10 excluding the most significant bit 20, and 22 denotes an inverter. 23,
24, 25 and 26 are AND circuits, 27, 28, 29 and 3
0, 31, and 32 are OR circuits. The data transfer control device 4 receives the data transfer request signal from the DMA device 3 and C
An appropriate control signal is output to the memory device 1 and the memory device 2 in response to an access request signal from another device such as a PU.

Only when "H" is input to the chip select signal lines 13 and 17 from the data transfer device 4, the memory devices 1 and 2 output "H" to the read enable signal lines 14 and 18 from the data transfer control device 4. Is input, reading is permitted, and when "L" is input, reading is prohibited. Similarly, the memory devices 1 and 2 are connected to the chip select signal lines 13 and 17 from the data transfer control device 4.
Only when "H" is input, writing is permitted when "H" is input to the write enable signal lines 15 and 19 from the data transfer control device 4, and writing is prohibited when "L" is input. The data read permission and data write permission for the same memory device and the data read permission for two memory devices at once are prohibited.

The operation of the data transfer device configured as described above will be described below. FIG. 3 shows a timing chart of the data transfer device shown in FIGS. As shown in FIG. 3, the transfer source data has an address "0xABC" which designates the entire memory area.
D ", and when transferring this data into the memory device 2, the DMA device 2 sends the address signal line 10" 0xABCD "to the data transfer control device 4 and the data read request signal line of the memory device 1. 6, "L" on the data write request signal line 7 of the memory device 1, "L" on the data read request signal line 8 of the memory device 2, and "H" on the data write request signal line 9 of the memory device 2. At this time, the data read request signal line 11 and the data write request signal line 1 for all memory areas are output.
2 outputs “L”.

On the other hand, the data transfer control device 4 applies “0x2BCD” to the address signal line 16 and the chip select signal line 13 to the memory device 1 and the memory device 2.
"H" is output to the data read enable signal line 14, "L" is output to the data write enable signal line 15, and data is taken out to the data signal line 5, and "H" is output to the chip select signal line 17. ", Data read enable signal line 18
"L" is output to the data write enable signal line 19, and "H" is output to the data write enable signal line 19, and the data taken out to the data signal line 5 is stored in the transfer destination.

As described above, the data extracted to the data signal line 5 from the entire memory area designating address “0xABCD” in the memory device 1 becomes the entire memory region designating address “0x2BCD” in the memory device 2. It is transferred in one cycle.

As described above, according to the present embodiment, two memory devices are prepared, and an access port having the same physical address is provided in each of the two memory devices. Data transfer between memories can be performed in half the time of the related art.

Hereinafter, a second embodiment of the present invention will be described with reference to the drawings. FIG. 4 is a diagram of a data transfer device according to a second embodiment of the present invention. In FIG. 4, 331, 332, 333,..., 33n are memory devices, 34 is a DMA device, 35 is a data transfer control device,
6 is a data signal line. 371, 372, 373,
, 37n are memory devices 331, 33 of the DMA device 34
33n, the data read request signal lines 381, 382, 383,..., 38n are the memory devices 331, 332, 333,.
A data write request signal line 39 for n is an address signal line for the entire memory area from the DMA device 34 and other devices such as the CPU to the data transfer control device 35. Reference numerals 40 and 41 denote a data read request signal line and a data write request signal line for the entire memory area from the DMA device 34 and other devices such as the CPU to the data transfer control device 35. 421, 422, 423, ...,
42n, chip select signal lines 431, 432, 433,..., 43n for the memory devices 331, 332, 333,.
n, a data read permission signal line for n, 441, 44
, 44n are memory devices 331,
, 33n, and 45 are data write enable signal lines, and 45 is a memory device 331, 332, 333,
.., 33n.

The data transfer device according to the present embodiment includes n memory devices 331, 332, 333, each of which is a power of two.
, 33n. These memory devices 331, 33
, 33n have the same memory space, and memories having the same physical address exist with each other. Assuming that the width of the address signal line 45 of each memory device is m bits and the logarithm of the number n of the memory devices with 2 as a base is n ′, that is, n ′ = log ₂ n, the address for all memory areas is The width of the signal line 39 is n '+ m bits. Further, when accessing the memory device with an address for all the memory regions, if the numerical value obtained by decoding the upper n ′ bits of the address signal line 39 is i, the data transfer control device 35 accesses the region in the memory device 33i. Control so that

FIG. 5 is a more detailed block diagram of the data transfer control device 35. In FIG. 5, reference numeral 46 denotes the upper n 'bits of the address signal line 39 for specifying the entire memory area;
7 is an m-bit lower bit address excluding the upper bit n 'from the address signal line 35; 48 is a decoder;
9, 50, 51, 52, 53, 54, 55, 56 are AN
D circuit, 57, 58, 59, 60, 61, 62, 63,
64, 65, 66, 67 and 68 are OR circuits. The data transfer control device 35 responds to a data transfer request signal from the DMA device 34 and an access request signal from another device such as a CPU, so that the memory devices 331, 332, 333,
.., 33n.

The memory devices 331, 332, 333,...
33n are the chip select signal lines 421, 422, 423,.
Only when “H” is input to the data transfer control device 3
5, the read enable signal lines 431, 432, 433,
When "H" is input to 43n, reading is permitted, and when "L" is input, reading is prohibited. Similarly, the memory devices 331, 332, 333,..., 33n are connected to the chip select signal lines 421, 4
Only when “H” is input to 22, 423,..., 42n, the write enable signal line 4
When "H" is input to 41, 442, 443,..., 44n, writing is permitted, and when "L" is input, writing is prohibited. Also, data read permission and data write permission for the same memory device and read permission for a plurality of memory devices at once are prohibited.

The operation of the data transfer device configured as described above will be described below. FIG. 6 shows a timing chart of the data transfer device of FIGS. As shown on the left side of the chart in FIG. 6, when the data of the transfer source is located at the address “0xABC” in the memory device and this data is transferred to the memory device 332 and the memory device 333, the DMA device 34 For the data transfer control device 35, "0" is input to the address signal line 39.
xABC ”,“ H ”on the data read request signal line 371 of the memory device 331,“ L ”on the data write request signal line 381 of the memory device 331,“ H ”on the data write request signal line 382 of the memory device 332, 33
2 is “L” on the data read request signal line 372, and “L” is on the data write request signal line 383 of the memory device 333.
H ”, the data read request signal line 3 of the memory device 333
“L” is output to 73. At this time, “L” is output to the data read request signal line 40 and the data write request signal line 41 for all memory areas. On the other hand, the data transfer control device 35
, 33n, "0xABC" is assigned to the address signal line 45, and the chip select signal line 42
1 to “H” and the data read enable signal line 431 to “H”.
H "," L "is output to the data write enable signal line 431, and data is taken out to the data signal line 36. At the same time, the chip select signal lines 422 and 423 are output.
"H", data read enable signal lines 432 and 43
3 to “L”, data write enable signal lines 442 and 4
"H" is output to 43, and the data taken out on the data signal line 36 is stored in the transfer destination.

As described above, the data extracted from the entire memory area designation address “0xABC” in the memory device 331 to the data signal line 36 is transferred to the address “0xABC” of the transfer destination memory devices 332 and 333 in one cycle. Will be transferred.

The transfer source data is stored in the memory device 331.
Of the memory device 33i (i = 2) except for the memory device 331.
When the transfer is performed within the range of (n) to (n), the DMA device 34 instructs the data transfer control device 35 to “0xCBA” on the address signal lines 39 for all memory areas, “H” on the data read request signal line 371, and other data. “L” is output to the data read request signal line 37i (i = 2 to n), “L” is output to the data write signal line 381, and “H” is output to the other data write request signal lines 38i (i = 2 to n). . At this time, the data read request signal line 4 for all memory areas
“L” is output to 0 and the data write request signal line 41.

As described above, the data extracted from the address “0xCBA” in the memory device 331 to the data signal line 36 is transferred to the address “0xCBA” in the destination memory device 33i (i = 2 to n) other than the memory device 331. "1
Transferred in cycles.

As described above, according to the present embodiment, by providing n memory devices of a power-of-two number and providing them with access ports having the same physical address, one memory device between different memory devices can be provided. The data transfer between the memory and the memory can be performed in 1 / (1 + i) time in the related art.

In the above-described first embodiment, the memory device divides the entire memory area into two equal parts, but the memory device may divide a part of the memory area into two equal parts. Also,
Also in the second embodiment, the memory device divides the entire memory area into n equal parts.
It goes without saying that it may be equally divided.

[0037]

As described above, according to the present invention, a data transfer control device is provided between a plurality of memory devices and a DMA device, and the data transfer control device operates between memory devices of different memory devices. In this configuration, data reading to the transfer source and data writing to the transfer destination are performed at the same time, so that one-to-one or one-to-many data transfer between memories between different memory devices can be performed. By performing data read and data write at once, high-speed data read and data write can be performed, which has a great effect on shortening the data transfer time.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a data transfer device according to a first embodiment of the present invention.

FIG. 2 is a detailed configuration diagram of a data transfer control device in the embodiment.

FIG. 3 is a timing chart at the time of data transfer in the embodiment.

FIG. 4 is a configuration diagram of a data transfer device according to a second embodiment of the present invention.

FIG. 5 is a detailed configuration diagram of a data transfer control device in the embodiment.

FIG. 6 is a timing chart at the time of data transfer in the embodiment.

FIG. 7 is a configuration diagram of a conventional data transfer device.

FIG. 8 is a timing chart at the time of conventional one-to-one memory-memory data transfer.

FIG. 9 is a timing chart at the time of a conventional one-to-many memory-memory data transfer.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 first memory device 2 second memory device 3 DMA device 4 data transfer control device 5 data signal line 10 address signal line 13 chip select signal line 14 data read enable signal line 15 data write enable signal line 16 address signal line 17 Chip select signal line 18 Data read enable signal line 19 Data write enable signal line

Claims (5)

[Claims] 1. A data transfer control device comprising: a DMA device; a plurality of memory devices; and a data transfer control device that controls data reading and data writing to the memory device, wherein the data transfer control device includes a memory between different memory devices. A data transfer apparatus characterized in that data transfer from a transfer source and data write to a transfer destination are simultaneously performed between the two. 2. A data transfer control device, wherein different memory devices each include a memory having the same physical address.
After outputting a valid address to the memory device, a chip select signal and a data read enable signal are output to the transfer source memory, and a chip select signal and a data write enable signal are output to the transfer destination memory. The data transfer device according to claim 1, wherein: 3. The data transfer control device includes means for dividing a memory by setting upper bits of a memory address as selector bits and setting remaining bits as valid address bits, and validating each of the divided memories. Means for connecting a data signal line corresponding to the address bit length, and means for simultaneously reading data from a transfer source and writing data to a transfer destination between memories having the same effective address bits. Item 3. The data transfer device according to item 1 or 2. 4. The data transfer device according to claim 1, wherein the data transfer device is configured to perform one-to-one memory-memory data transfer between different memory devices. . 5. The memory device according to claim 1, wherein one-to-many memory-to-memory data transfer is performed from one memory device to another plurality of memory devices. 2. The data transfer device according to claim 1.