JPH04116750A - Dma memory transfer device - Google Patents

Abstract

PURPOSE:To realize memory-memory transfer in one cycle by setting a write start address in a counter in the initialization of CPU, providing a DMA bank register and a DMA selector and selectively giving a DACK signal to a transfer destination in the initialization of CPU. CONSTITUTION:The data buses 5 of plural bank memories 10-15 are connected to the same data buses of CPU 1 and an address means 20 is provided. It sets the start address of a transfer source address in the initialization of CPU 1 and it is increased at the timing of the acknowledgement signal (DACK) of DMAC, whereby it gives the address. DMAC initializes the start address of the transfer source by CPU 1, it is increased at the timing of the acknowledgement signal (DACK) and gives the address. Thus, memory-memory transfer is realized in one cycle only by permitting one DMAC to designate the transfer source or transfer destination address.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to high-speed data transfer between memories, which is used in computers, word processors, etc., and is controlled by a direct memory access (hereinafter referred to as DMA) controller.

Conventional technology In recent years, data transfer between computers, word processors, etc. (such as floppy disk drives,
When transferring data from a hard disk drive, etc., it is generally possible to transfer data at high speed without using the CPU.
This is done using the A controller. The DMA controller is capable of transferring memory and memory from the input/output port (hereinafter referred to as I10).The transfer destination address (in the case of memory memory transfer, the transfer source address must also be specified) is automatically transferred after that. The address is incremented, and when the set number of data transfers is completed, the end is notified.

Furthermore, the current situation is that the amount of memory used in computers and the like is increasing in accordance with the capacity of applications used.

Therefore, one of the methods of memory control circuits used in personal computers and the like in recent years is an interleave method.

When using refresh memory such as DRAM for high-speed operation, this method divides the memory into several banks and allows each to operate independently, so that one memory access cycle is followed by another bank. If it is a memory access cycle to another bank, the recovery time for the previous bank is included in the access cycle to another bank.This method attempts to ensure high-speed operation for applications that use a large amount of memory. It is something.

FIG. 4 is a block diagram showing the configuration of a conventional DMA memory transfer device using an interleave method for two-bank memory transfer. As can be seen from the figure, the two banks are independent of each other and can operate independently.

FIG. 5 is a timing chart showing the operation.

In the figure, two cycles of the central processing unit (hereinafter referred to as CPU) correspond to one cycle of the memory itself. In other words, if the memory of bank 1 is precharged while accessing bank O, and then there is an access to bank 1 immediately, the memory of bank 0 will be precharged while accessing bank 1. It is an action that earns Bunochashi.

In other words, when interleaving is hit, the CPU always operates with 0 waits.

Problems to be Solved by the Invention In such a conventional DMA memory transfer method, even if the speed is increased by using interleaving, as shown in FIG. Due to the unreasonableness of using two controller channels and the fact that the transfer source memory address and transfer destination memory address must be output to the bus as shown in Figure 6, the number of cycles is 2.
The problem was that the transfer time took twice as long.

Furthermore, although memory is divided into several banks and each bank can be operated independently, current memory transfer using DMA has a large waste of accessing only one bank in one cycle. .

The present invention solves the above problem, and aims to provide a DMA memory transfer device in which one DMAC accesses both the transfer source and transfer destination banks in one cycle.

Means for Solving the Problems In order to achieve the above object, the present invention provides a central processing unit CPU having a small number of data buses for inputting and outputting data, a plurality of independent memory banks sharing the data bus, The CPU inputs and outputs the data of the memory bank.
and a direct memory access controller DMAC that independently controls the DM.
Addressing means is provided for generating an address signal that is incremented at the timing of the permission signal DACK output by the AC, and the CPU specifies the memory bank to be used in the initial setting operation, and the start address of the address signal to be used for the DMAC and the address. After setting the start address of the address output by the means, the DMAC sends the permission signal DACK to the transfer source memory bank.
and an address, and while incrementing the address at the timing of the DACK, read out the transfer source data sequentially from the start address to the data bus,
The transfer destination memory bank inputs the DACK and the address output of the address means, and the address is the DACK.
The DMA memory transfer device is incremented at the timing of ACK so that the data is taken in in synchronization with the transfer source putting the data on the data bus, and written sequentially from the start address.

According to the above-described configuration, the present invention transfers the data in the source bank to the destination bank via the I10 terminal of the data bus of the CPU (the CPU does not read it), so that the memory transfer is performed as if it were a memory 110 transfer. is executed like this. Due to the initial condition setting operation of the CPU, the DMA
The start address of the address output by C and the start address of the address output by the address means are set. After the setting, the CPU releases the bus to the DMAC, leaves control, and uses the DM
The AC inputs an address signal and a permission signal DACK to the transfer source memory bank, and sequentially outputs data to the data bus from the start address at an address that is incremented at the timing of DACK, and the transfer destination memory bank receives the incremented address of the address means. is given, the data on the bus is taken in and recorded sequentially from the starting address.

Embodiment Hereinafter, a DMA memory transfer device according to an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of a DMA memory transfer device according to an embodiment of the present invention, and FIG. 2 is a block diagram showing the configuration of a memory bank according to the embodiment of the present invention. To explain the components in FIGS. 1 and 2, 1 is a central processing unit CPU equipped with a data bus 3, and 2 is a DMAC that can control data input/output of bank memories 10 to 15 independently of the CPU. It is. Bank memories 10 to 15 are memories that can each operate independently (control is independent), and in intermemory transfer, any one of them serves as the transfer source and one of the others serves as the transfer destination. The counter 16 with a load function in the address means 20 is
When the PU is initialized, the counter is loaded with the initial count value and set, and the count value is output to the address selector 17 as an address. Selector 1
7 is the system address bus and the output 2 of the counter 16.
The type of input is switched by a permission signal 9 from the DMA controller 2, and a local address 19 is output. 21 is a memory controller circuit that receives access from the CPU and DMA controller and generates RAS, CAS, and commands to the memory. Also, 6 is which bank is accessed from the CPU via I10.
DMA bank register to set whether to perform A transfer, 7
is D according to the value set in the DMA bank register.
A DACK signal is sent to each memory bank at the timing of the permission signal (DACK signal) 8 from the MA controller.
This is the MA bank selector.

The related operations of each component of the device made up of the above components will be described below using an example in which data is transferred from a transfer source memory to a transfer destination memory.

Assuming that the transfer source memory bank is 10 and the transfer destination memory bank is 13, the start address of the transfer destination memory 13 is set as an initial value in the load function counter 16 by the CPU. DMA bank register 6 contains memory bank 1.
Write that code to select 3. Further, the DMA controller 2 is set with the mode designation of the memory 110 transfer and the transfer source address by the CPU. At this time, the transfer destination memory 13 is treated as Ilo, and the DMA controller 2
Transfer request signal by software (channel used is 1)
1) is output, the DMA controller 2 acquires the bus, and then a permission signal 4 (DACK) is returned. D
The MA bank selector 7 decodes the code set in the DMA bank register 6 and sends a transfer request signal 9 (
local DACK). This signal is used to switch the selector 17, and the initial value of the counter 16 of the counter with load function is output to the local address of the transfer destination memory 13. Further, the DMA controller 2 outputs a transfer source address to the system address bus.

Through the above operations, memory bank a outputs data, and memory bank e writes data in response to the DACK signal.

On the other hand, when the first transfer cycle is completed and the permission signal is negated, the counter 16 is incremented by 1 at that edge, and the counter output 18 becomes the value plus 1. When the second transfer starts, an address incremented by 1 from the start address is output to the local address 19 using the same procedure as the first transfer, and an address incremented by 1 by the DMA controller 2 is output to the address bus, and the second cycle ends. do. Thereafter, the address bus and local address bus are similarly incremented along with the transfer cycle.
The desired memory memory transfer is completed.

As described above, according to the DMA memory transfer device of the embodiment of the present invention, a counter with a load function is provided in the memory bank as a transfer destination address generating means, a write start address is set in the counter in the initial setting of the CPU, and the DMAC D
The timing of the ACK signal shall be incremented in accordance with the address of the transfer source, and a DMA bank register and a DMA selector shall be provided as bank selection means, and the DACK signal shall be selectively given to the transfer destination by the initial setting of the CPU. By doing this, DMA C can perform memory transfer simply by specifying the transfer source address.
One DMAC enables memory transfer in one cycle.

Note that it goes without saying that the transfer source address may be set by a counter and the transfer destination address may be set by DMAC.

Effects of the Invention As is clear from the embodiments described above, the data buses of a plurality of bank memories are connected to the same data path of the CPU, and an address means is provided, and the address means is used to specify the transfer source (or transfer destination) in the initial setting of the CPU. ) The start address of the address is set, the timing of the DMAC permission signal (DACK) is incremented to give the address, and the DMAC is initialized with the start address of the transfer source (or transfer destination) by the CPU.
By incrementing the address at the timing of the permission signal (DACK), memory transfer can be performed in one cycle simply by the DMAC specifying the transfer source or transfer destination address.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a DMA memory transfer device according to an embodiment of the present invention, FIG. 2 is a block diagram showing the configuration of a memory bank according to an embodiment of the present invention, and FIG. 3 is a block diagram showing the configuration of a memory bank according to an embodiment of the present invention. FIG. 4 is a block diagram showing the configuration of a DMA memory transfer device using the conventional interleaving method. FIG. 5 is a timing chart showing the memory transfer operation of the same device. FIG. 6 is a timing chart showing the operation of the example. is a timing chart showing the operation of memory 110 transfer in the same device. 1...Central processing unit CPU, 2...Direct memory controller DMACl3...
Address bus, 5... Data bus, 8, 9...
. . . Permission signal DACK, 10 to 15 . . . Memory bank, 20 . . . Address means. Name of agent: Patent attorney Haruaki Koba et al. 26 Figure 2O-7)

Claims (4)

[Claims] (1) A central processing unit CPU having at least a data bus for inputting and outputting data, a plurality of independent memory banks that share the data bus, and controlling data input and output of the memory banks independently of the CPU. In a memory device comprising a direct memory access controller DMAC, a permission signal DAC output from the DMAC;
An address means for generating an address signal that is incremented at timing K is provided, and the CPU specifies a memory bank to be used in the initial setting operation, a start address of the address signal output from the DMAC, and an address output from the address means. After setting the start address, the DMAC supplies the enable signal DACK and the address to the transfer source memory bank, and the DAC
While incrementing the address at timing K, the transfer source data is read out sequentially from the start address to the data bus, and the transfer destination memory bank is read out to the data bus from the start address.
inputting ACK and the address output of the address means;
A DMA memory transfer device in which the address is incremented at the timing of the DACK, thereby taking in the data in synchronization with the transfer source putting the data on the data bus, and writing the data sequentially from the start address. (2) The address means is composed of a counter with a load function and an address selector, the counter with a load function outputs a count value as an address, a count start value is set in the initial setting of the CPU, and the count output is the same as the DACK signal. The address selector receives the output of the counter and the address of the address bus, and supplies the count output to the memory instead of the address of the address bus according to the timing of the DACK signal. DM described in section (1)
A memory transfer device. (3) The DM according to claim (1) or (2), wherein the DMAC controls the address of the transfer destination memory bank, and the address means controls the address of the transfer source memory bank.
A memory transfer device. (4) The DMA memory transfer device according to any one of claims (1) to (3), wherein a DMA bank register and a DMA bank selector are provided, and the DMA bank register is set with a code specifying a memory bank to be used in the initial setting of the CPU. DMA memory transfer device, wherein the DMA bank selector outputs a DACK signal to a memory bank designated by the bank register.