JPH01260559A - Microcomputer system - Google Patents

Abstract

PURPOSE:To efficiently perform the development of a program by providing an additional circuit for DMA (direct memory access) transfer in which data transfer from a memory having an address unaccessible directly from a CPU to the memory having the address accessible directly from the CPU is enabled. CONSTITUTION:The additional circuit 7 for the DMA transfer is connected between the CPU 1 and a DMA controller 2 via an address bus 3 and a data bus 6, etc., and a main memory 8, an extension memory 9 are connected to the CPU 1, the DMA controller 2, and the additional circuit 7 for the DMA transfer via the address bus 3 and the data bus 6. And the additional circuit 7 for the DMA transfer is constituted so that the data transfer can be performed from the range 9a of the extension memory 9 having the address unaccessible directly from the CPU 1 to the range 8a secured in advance of the main memory 8 accessible directly via the data bus 6. In such a way, it is possible to realize the direct access of data from the CPU 1 by a simple program.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to data transfer in a microcomputer system, and relates to data transfer between a CPU (central processing unit) and a memory.
The present invention relates to a microcomputer system comprising an MA (direct memory access) controller capable of memory transfer, a memory having an address that can be directly accessed by a CPU, and a memory having an address that cannot be directly accessed by the CPU.

[Conventional technology]

Conventionally, this type of microcomputer system has a fourth
As shown in the figure, a DMA controller 2 and a memory 4.5 are connected to the CPU via an address bus 3. Along with this, a DMA controller 2, a memory 4. '5 and CP
The data bus 6 is connected to the UI. This is a device that not only transfers data between the CPU 1 and memories 4 and 5, but also uses the DMA controller 2 to transfer data in a predetermined range of memory to another range at high speed without going through the CPU 1. It is. Therefore, the contents of the memories 4 and 5, which are normally inaccessible from the CPU, can be transferred to a range that can be directly accessed.・MA controller 2 like this
A microcomputer system using a CP uses a floppy disk, hard disk, etc. to expand a large capacity memory that cannot normally be accessed by a microcomputer, and uses a CP [11] to provide extremely high-speed take transfer. It can be applied to whatever you do.

[Invention or problem to be solved]

However, conventionally, each time it was desired to read a take from the extended memory, the register of the MΔ controller 2 had to be changed, which was troublesome. In addition, the user had to manage the memory location of the take transfer destination, the transfer high I-number, etc. one by one. Therefore, when adding new hardware ((() and expanding memory),
There was a problem in that it was troublesome to use.

The present invention has been made in consideration of the above-mentioned problems, and an object of the present invention is to provide a microcomputer system that can eliminate administrative hassles and make program development more efficient.

[Means for solving the problem] Means for achieving the above object of the present invention are C
I) With U, memory-memory transfer is possible and MΔcon 1
- a microcomputer system consisting of a memory having an address which can be accessed directly from the MiJ CPU, and a memory having an address which cannot be directly accessed from the CF)U;
The present invention relates to a microcomputer system characterized in that it is provided with an additional circuit for DMA transfer that enables data transfer from a memory having an address that cannot be directly accessed to the memory having an address that can be directly accessed.

[Effect]

” - In the configuration described above, for DMA transfer ((l adder circuit is installed B
] This makes it possible to transfer data from a memory having an address that cannot be directly accessed by the CPU to a memory having an address that can be directly accessed, thereby allowing direct access of data from the CPU.

(Embodiment) Hereinafter, an embodiment of the present invention will be described with reference to FIGS. 1, 7, and 2. Parts that are the same as those in the prior art are denoted by the same reference numerals, and the explanation thereof will be omitted.

7 is a DMA transfer input circuit, which connects the CPUI and DMA controller via address bus 3, data bus 6, etc.
- Connected between roller 2.

8 is a main memory, and 9 is an expansion memory, which are connected via an address bus 3 and a data bus 6 to a CPU I, a DMA controller 2, and an additional circuit 7 for DMA transfer. The DMA transfer adder circuit 7 uses a range 9 of the extended memory 9 that has addresses that cannot be accessed directly from the CPUI.
It is possible to transfer data via the data bus 6 to a pre-secured range 8a of the main memory 8 that can be accessed directly from the main memory 8a.

According to Fig. 2, the configuration of the additional circuit for DMA transfer and C
I) The connection relationship between tJ 1 and DMA controller 2 will be explained in detail. The additional circuit 7 for DMA transfer is connected to the boat 7.
1, a write module 72, and a latch 73. C.P.
UI and boat 71, boat 71 and writing module 72
, the write module 72 and the DMA controller 2 are connected by an address bus 3, respectively. The launch 73 is connected to the CPUI and the DMA controller 1 and 2 via the data bus 6. 10 is write module 2 and CP
Take the AND of the control 1 signal with U
This is an AND circuit for controlling the writing of roller 2.

Next, the operation of the embodiment with the above configuration will be explained with reference to the time chart I in FIG.

To transfer data from the extended memory 9 to the main memory 8, first, in mode (2), the address on the extended memory 9 to be read is output from the CPUI to the boat 71. This is the address assigned to A tobacco boat 7]. Beau 1-71 @
With ll'+MU, Uchi 73 launches the data. Next, the data latched by the latch 73 in mode (2) is written to the DMA address register of the DMA controller 2. B is an address register of the DMA controller 2. After this writing, the output of latch 73 becomes high impedance. In mode ■, data for starting DMA is written to the DMA software start register.

C is an address on the extended memory 9, D is a rough 1-ware DMA start register of the DMA controller 2, and E is rough 1-ware DMA start data. And DM
Due to the capabilities of the Δ controller 1-roller 2, a data transfer from, for example, range 9a of extended memory 9 to range 8a of main memory 8 is effected via data bus 6. At this time, main memory 8
The address indicating which range of data should be transferred is
First, write each to the register of DMA controller 2.

However, once written, there is no need to change it. When the DMA transfer (direct memory access transfer) is completed, the DMA controller 2 generates an incrab 1-(INT) signal, and the CPU resumes normal control. In this way, the DMA transfer additional circuit 7 transfers the entire data in the range 9a to be read from the extended memory 9 to the pre-secured range 8a in the main memory 8 under the control 6 of the CPUI. Therefore, the data transferred to range 8a can be directly read from the CPUI. In this way, to specify the address of the data you want to read from the extended memory 9, -
You can access it just by entering the text.

〔Effect of the invention〕

As described above, the present invention provides a microcomputer system that allows access from an expanded memory having addresses that cannot be accessed directly from a CPU by simple programming without considering hardware. can do.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a microcomputer system showing one embodiment of the present invention, and FIG. 2 is a DM shown in FIG.
FIG. 3 is a block diagram showing in detail the additional circuit 7 for A transfer, and FIG. 3 is a block diagram of a conventional microcomputer system. be.

Claims (1)

[Claims] In a microcomputer system comprising a CPU, a DMA controller capable of memory-to-memory transfer, a memory having an address directly accessible from the CPU, and a memory having an address not directly accessible from the CPU, 1. A microcomputer system comprising an additional circuit for DMA transfer that enables data transfer from a memory having an address that cannot be accessed to a memory having an address that can be directly accessed.