JPS5960787A - Memory access system - Google Patents

Abstract

PURPOSE:To eliminate a time delay with an access to a memory space by using a decoder to select a row address and another decoder to select column addresses of all memory arrays in accordance with the contents of a bank register. CONSTITUTION:It is possible to perform decoding with no time delay since no condition is needed to decide whether the upper two bits of an address are equal to ''00'' when a row address signal RAS is generated. However both R-DEC1 and R-DEC2 deliver output signals at a time, and no effect is given to the address selection of a memory since the selection is done by a column address signal. A column address signal CAS decides the lower two bits of address and is furthermore decoded by a decoder DEC via a logical circuit which decides the validity/ invalidity of the contents of a bank register. Therefore the output is slower than the signal RAS, and a column address signal selects a memory array although a dot OR is given to the output side of the memory array. This ensures a normal access operation.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to an access method that eliminates time delay when accessing memory space.

(2) Prior art and problems: In order to effectively utilize the memory space of the computer, space expansion registers (commonly called bank registers) are used.
It is used to have multiple memory spaces as shown in the figure. For example, a processor uses a 16-bit address tWN (
Of the addressed memory space, 16KW from the beginning is used as the common part GM, and the remaining 48KW is used for banks BNKO and BNKl.

..., the bank to be used is specified by the bank register BKH, and the address within the bank is specified by the address information from the processor. In this case, the specific means of specifying is the second
This was done as shown in the figure. In FIG. 2, the upper two pittons of the 16 bits of address information are judged, and if it is "oo", the common part CM is accessed, and 16KW of array MAD, which is the common part of the memory array, is accessed. When the upper bit of the address is other than "00", the contents of the bank register BKH and the upper bit of the address are decoded together by the decoder DEC, and the memory array M
Specify A1 to MAn. When using dynamic memory, the access signals are RAS (row access signal),
Two types of GAS and C column access signals are applied separately, and the addresses are determined by the falling edge of the RAS and GAS signals, respectively, and latched into the memory specified by the decoder output. (The memory selection signal of the decoder output is RAS
, /cAs timing signal punched RAS
, GAS signal The time chart of each signal in the operation above is shown in FIG. Check the upper 2 bits of address information on the address bus and check the bank register BNK.
A gate circuit is required to determine whether the contents of is valid or invalid, and the address judgment time ADT until input to the decoder circuit and the decode time DOT until output to the decoder circuit are the memory access time. Delay (3
) OBJECTS OF THE INVENTION It is an object of the present invention to provide an access method which can overcome the above-mentioned drawbacks and avoid time delays when accessing memory space is busy.

(4) Development of the invention The configuration of the present invention to achieve the above-mentioned object is to divide the memory space into one common part and a plurality of banks17, and to specify the bank using a bank register7. In the method of accessing the memory, a dynamic memory formed of a plurality of memory arrays is used as the memory, and a decoder for selecting a row address of the memory array including the common part from the addressing bits, and the contents of the bank register and the The memory array is equipped with a decoder for selecting the row address of an unused memory array as a bank based on the address designation bit, and a decoder for selecting the column address of the entire memory array based on the contents of the bank register. It is accessing memory while specifying it.

(5) Embodiment of the invention FIG. 4 is a block diagram showing an embodiment of the invention. In Fig. 4, the same reference numerals as in Fig. 2 indicate the same things, and R
-101 is a decoder (memory array MAO is used as a common part) for selecting the row address RAS of the memory array MAOO by the upper two bits of the address designating bits, and R-DEC2 is the bank register BNK.
A decoder for selecting a row address signal of another array number based on the contents of and the upper two bits of the address (arrays other than memory array MAD are used as binders), C
-DEC indicates a decoder for selecting the column address of each bank from the contents of the bank register BNK. The upper two bits of the address information from the processor are sent to the decoder R-
Decoded by DIG 1 and row address signal RAS
Generate O. For example, the 4 bits of bank register B14K and the upper 2 bits of the address are sent to decoder R-D.
Row address signal RASI decoded by KCj 2
~RASnY is generated. When this row address signal RAS is generated, there is no condition for determining whether the upper two bits of the address are ``00'' or not, so decoding can be performed without time delay. However, R-DEG I and R-DEC2
Both of them will issue output signals at the same time, but since the selection is made by a column address signal, which will be described later, it does not affect memory address selection. The column address signal GAS determines the upper two pitons of the address and sends it to the bank register BNK.
The output is later than that of the row address signal RAS because it is sequentially decoded by the decoder DECK via the logic circuit LG which determines whether the contents of are valid or invalid. Therefore, even if all the output sides of the memory array are dot-ORed, the column address signal selects one memory array, so the access operation can be performed normally. (Because the output of the memory is enabled by the column address select C1AS) FIG. 5 is a time chart similar to that of FIG. Because it is obtained early by the DEC2, there is no time delay for determining the upper bits of address information and generating a valid address, making high-speed memory access possible.The row address signal RAS activates the memory array. Since the number is within 2, an increase in the required power has almost no effect.If the row address signal RA
Even if the row address signal is input to all memory arrays at the same time, the column address signal CAS
Since all memories are activated by the row address signal, logically normal operation is possible and the time delay of the address judgment circuit can be saved.
The power consumption of the entire memory becomes enormous. Therefore, a decoder circuit that generates a row address signal is necessary.

In this way, according to J, it is possible to access space without time delay.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram of conventional memory access, FIG. 2 is a configuration diagram of a conventional memory access circuit, FIG. 3 is a time chart of FIG. 2, FIG. 4 is a configuration diagram of an embodiment of the present invention, and FIG. 5 is the time chart of FIG. GM...Common section BNKO, BNKl...
Bank BKR...Bank register MAO, MA
I...Memoryao R-DEG1, R-DI12...
・Row address signal decoder C-DEC・-・Column address signal decoder Patent applicant: Fujitsu Limited Agent: Eisuke Tsuchi Suzuki, patent attorney

Claims (1)

[Claims] In a method in which a memory space is divided into one common part and a plurality of banks, and the memory is accessed while specifying the bank using a bank register, the memory is formed of a plurality of memory arrays. Using dynamic memory, a decoder for selecting a row address of a memory array including the common part according to addressing, and a memory array not used for the common part as a bank according to the contents of a bank register and the addressing bits. A memory access method characterized by having a decoder for selecting the row address and a decoder for selecting the column address of the entire memory array according to the contents of the bank register, and accessing the memory while specifying the memory array. .