JPH06139371A - Microcomputer - Google Patents

Abstract

PURPOSE:To improve the scale of the facilitating circuit of the design of a connection circuit, the reduction of a board and access efficienty by providing a means discriminating whether an access is the one to a memory or other acesses or not on a microcomputer main body. CONSTITUTION:When a microcomputer performs an access to an external memory, whether the access object address value generated in an address modifier 208 is within a DRAM area set to an address/map setting circuit 203 or not is discriminated by an address comparison circuit 204. In this case, the combination of the multiplex of a low address and a column address is set to the address map setting area 203 in advance. When the access object is judged to be the DRAM area by the comparison result of the address comparison circuit 204, the address is multiplexed by the address constitution of the DRAM selected by the setting of the address/map setting area 203 by an address multiplexer 206 and the address is outputted to an address bus 205.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer, and more particularly, to a dynamic random access memory (DRAM) connection function, in which a row address and a column address are output from the same address output terminal when accessing the DRAM. The present invention relates to a microcomputer that outputs in time division.

[0002]

2. Description of the Related Art A DRAM adopts an address multiplex system in which an address is divided and input twice. Each address is input to DRAM RAS (inverted value)
The signal and the CAS (inverted value) signal are taken in at each falling edge (latch).

First, an address latched at the falling edge of the RAS (inverted value) signal is a row address (hereinafter referred to as a row address), and then an address latched by a CAS (inverted value) signal is a column address (hereinafter referred to as a column address). Called address)
Has become.

A conventional microcomputer having a built-in DRAM connection function has an RA when connecting to the DRAM.
The output signal from the microcomputer could be used as it is for the S (inverted value) signal and the CAS (inverted value) signal.

Two examples of conventional microcomputers having a built-in DRAM connection function are shown in FIGS. Here, microcomputers V55 (FIG. 11) and V35 (FIG. 13) manufactured by NEC Corporation are shown as an example.

FIG. 11 shows a device of a conventional microcomputer body V55 (hereinafter referred to as CPU body) 700. V55 CPU main body 700,
An execution unit (EXU) 801 and a bus control unit (BCU) 802 are built in.

An address modifier (ADM) 808 in the bus control unit 802 generates an address signal according to the information from the address latch 820 or the address register 821 and outputs it to the internal address bus 805. Lower 16 of address bus 805
Bit signals (D0 to D15) are address / data
Internal data bus 803 by multiplexer 806
Data signal is output to the address / data multiplex bus 807.

The wait control circuit 809 can insert a wait cycle into the bus timing by setting the control register by software. In addition, the status controller 810 outputs a bus status signal.

Next, regarding the configuration of the connection circuit example of the conventional microcomputer and the memory of FIG. 11, V5 of FIG.
A description will be given based on the example of No. 5. In FIG. 10, V in FIG.
From the CPU main body 700 of 55, a data read strobe (RD) signal 70 is generated when an external memory is accessed.
1, high byte data write strobe signal (WRH) 702, low byte data write strobe signal (WRL) 703, address strobe signal (ASTB) 704, and DRAM row address latch timing Signal (RAS) 706 and A1
Address signals 705 from 6 to A23, and AD0
Each signal of the address / data multiplex signal 708 from AD15 to AD15 is output.

When connecting to the DRAM and the SRAM, as shown in FIG.
The output of the read strobe signal 701 is input to the OE (inverted value) terminal of each memory block, and the high byte data write strobe signal 702 is input to the upper bank D (dynamic) RAM block 720 and the upper bank S (static) RAM. The row byte data write strobe signal 703 is input to the WE (inverted value) terminal of the block 740 and the WU (inverted value) terminal of the lower bank DRAM block 730 and the lower bank SRAM block 750. In addition, the CS (inverted value) terminal of SRAM is
SRAM chip select signal (SRAMCS signal) generated by the chip select signal generation (CS) circuit 710
Enter 711.

RAS (inverted value) of upper bank DRAM block 720 and lower bank DRAM block 730
The input signal to the terminal is the DRAM row address latch timing signal 70 from the CPU body 700 of V55.
6 is input as it is, and the DRAM column address latch timing signal (DRAM CAS signal) 712 generated by the chip select signal generation circuit 710 is input as the input signal to the CAS (inverted value) terminal.

The address / data multiplex signal 708 of the V55 CPU main body 700 outputs the address signal and the data signal in a time division manner. Therefore, an address latch circuit 770 is provided externally to generate a latch address signal 771. There is a need. This output signal may be used as the address signal to the SRAMs 740 and 750.
Since it is necessary to multiplex the row address signal and the column address signal and input the address signals to the M720 and 730, the row address / column address switching circuit 760 is used in combination with the row address / column address switching circuit 760. It was necessary to convert the column address multiplex signal 761 and input it to the address input terminal of the DRAM.

As for the address data, the address data of D0 to D7 are transferred to the lower order through the data buffer 780, and the address data of D8 to
The address data of D15 is input to each upper memory.

Next, an example of the conventional microcomputer shown in FIG. 13 will be described. The CPU main body 900 in FIG. 13 is [V35].

An execution unit 1001 and a bus control unit 1002 are formed in the V35 CPU main body 900. An address modifier (ADM) 1008 in the bus control unit 1002 generates an address signal according to the information from the address latch 1020 or the address register 1021 and outputs it to the internal address bus 1022.

The 20-bit address signal output to the internal address bus is the address multiplexer 1006.
Thus, the signals are multiplexed and output to the ten address buses 1005 of A9 / A1 to A19 and the A0 and A18 / UBE (inverted value) terminals. The signal on the internal data bus 1007 is output as it is as a data bus signal.

The wait control circuit 1009 can insert a wait cycle into the bus timing by setting the control register by software. Also,
A bus status signal is output from the status controller 1010.

Next, regarding the configuration of the connection circuit example of the conventional microcomputer and the memory shown in FIG. 13, the V3 shown in FIG.
A description will be given based on the example of No. 5. In FIG. 12, C of V35
From the PU body 900, a read / write cycle identification signal 901 at the time of external memory access,
Outputs A18 / upper byte enable multiplex signal 902, lower memory bank select signal 903, memory strobe signal 904, address multiplex signal 905, memory request signal 906, and data bus signal 907. To be done. Also, D
REFR that outputs DRAM refresh pulse signal (909) at refresh timing when RAM is connected
A Q (inverted value) terminal is prepared.

When connecting to DRAM and SRAM, as shown in FIG. 12, A18 / upper byte enable multiplex signal 902, lower memory bank select signal 903, memory strobe signal from CPU body 900 of V35 904 and read cycle / write cycle identification signal 901, upper bank read signal (OOE (inverted value)), upper bank write signal (OWE (inverted value)), lower bank read signal (EOE ( 4) of the lower bank write signal (EWE (inverted value)) and the upper bank read signal (OOE (inverted value)) to the upper bank DRA.
M block 920 and upper bank SRAM block 940
Of the upper bank write signal (O
WE (inverted value) is input to each WE (inverted value) terminal. The lower bank read signal (EOE (inverted value)) is input to the OE (inverted value) terminals of the lower bank DRAM block 930 and the lower bank SRAM block 950, and the lower bank write signal (EWE (inverted value)) is set to W.
Input to the E (inverted value) terminal.

The SRAM chip select signal 911 from the chip select signal generation circuit 910 is input to the CS (inverted value) terminal of the SRAM.

RAS (inverted value) of upper bank DRAM block 920 and lower bank DRAM block 930
The input signal to the terminal is a signal obtained by ANDing the memory request signal 906 from the CPU body 900 of V35 and the DRAM refresh pulse signal 909, and the input signal to the CAS (inverted value) terminal is the chip. Input the DRAM column address latch timing signal 912 generated by the select signal generation circuit 910.

In addition, the 2-input NAND gate 960 has 6
There is one NOR gate 961. In addition, there is one inverter 962. Other details are the same as in FIG.

As the address multiplex signal 905 of the CPU main body 900 of V35, an 18-bit address signal of A1 to A18 is output from 9 terminals twice in a time division manner. A19 is output as it is. D
To input the address signal to the RAM, the address multiplex signal 905 is input as it is, the upper address output in the first half is used as the row address of the DRAM, and the lower address output in the latter half is the column of the DRAM.・ It could be used as an address. However, S
As an address input signal to the RAM, a higher-order address signal generated by the output of the address multiplex signal 905 from the CPU body 900 of V35 is latched by the higher-order address latch circuit 970 and taken into the SRAM at the same timing as the lower-order address signal. I had to go.

Since the address signal output of V35 is output by address / address multiplex, V35
The memory cycle of 35 includes a first state for outputting an upper address (one cycle of the first operation clock after the bus cycle is activated is called a first state. The same applies hereinafter) and a second state for outputting a lower address. , Read data /
At least three states of the third state for writing were required.

[0025]

The above-mentioned conventional microcomputer uses the DRAM and S as external memories.
When connecting a RAM, when the address signal output from the CPU is an address / data multiplex signal, an address latch circuit, row address / column
The address switching circuit and the data bus buffer circuit, and when the address signal output from the CPU body is the address multiplex signal, the higher address
Each of the latch circuits is required as an external circuit, which makes the design difficult, the design scale becomes large, the circuit becomes complicated, and the board becomes large.

When the address signal output from the CPU main body is an address multiplex signal, the memory cycle outputs a first state in which the upper address is output, a second state in which the lower address is output, and data read / write.
Since there are at least three states of the third state for writing, one memory is required even when accessing SRAM.
There is a drawback that the processing efficiency of the microcomputer is lowered because the cycle takes 3 states.

An object of the present invention is to solve the above drawbacks and to provide a microcomputer capable of easily designing a circuit for connecting a microcomputer main body and a memory, reducing the circuit scale, reducing the board, and efficiently accessing the memory. Especially.

[0028]

The first structure of the present invention is as follows.
In a microcomputer having a microcomputer body and a plurality of address terminals for outputting an address to the outside, a row address timing signal of a dynamic random access memory and a CAS column
The microcomputer main body has a function of outputting an address / timing signal, and the microcomputer main body has means for discriminating whether the memory is accessed or not, and the address information for each access is set to 1 at the address terminal.
It is characterized in that it has a multiplex for controlling whether to output the information once or to divide and output the address information to a specific address terminal twice or more.

The second microcomputer configuration of the present invention is such that the address configuration of the DRAM and the setting area of the assigned address range, the means for comparing the set address range and the address to be accessed, and the address are multi-checked from the comparison result. It features a built-in address multiplexer that has the function of switching whether or not to perform plexing.

[0030]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 2 is a block diagram showing a microcomputer main body according to an embodiment of the present invention.

In FIG. 2, the inside of the microcomputer main body 100 of this embodiment has an execution unit 201 and a bus control unit 202.
Is configured. Bus control unit 20
2 includes an address map setting area 203 for designating an address configuration and an allocation area of the DRAM, and an address comparison circuit 2 for determining whether an access target is a DRAM area set in the address map setting area 203.
04, SRA according to the determination result of the address comparison circuit 204
When accessing M, all bits of the address are output at once, and D
At the time of RAM access, an address multiplexer 206 that multiplexes and outputs a row address and a column address with the address configuration set in the address map setting area 203, a wait control circuit 209 that controls the timing of the bus state, and a status signal Is provided, and an address modifier 208 for generating a physical address from an address latch and an address register is configured.

Next, the configuration of the connection circuit example of the microcomputer and the memory of this embodiment will be described based on the example of FIG. In FIG. 1, a microcomputer main body 1
00, the data read strobe signal 101, WRH from the RD (inverted value) terminal at the time of memory access.
High byte data write strobe signal 102 from the (inverted value) terminal and low from the WRL (inverted value) terminal
Byte data write strobe signal 103, CA
The S (inverted value) terminal outputs the DRAM column address latch timing signal (104), the RAS (inverted value) terminal outputs the DRAM row address latch timing signal 106 control signals, and the address signal 105, Data bus signal 107 becomes active.

DRAM and SRAM as external memory
Data read strobe signal 1 when connecting
01 is input to the OE (inverted value) terminal of each memory block, and high byte data write strobe signal 1
02 is input to the WE (inverted value) terminals of the upper bank DRAM block 120 and the upper bank SRAM block 140, and the row byte data write strobe signal 1 is input.
03 is input to the WE (inverted value) terminals of the lower bank DRAM block 130 and the lower bank SRAM block 150. In addition, the CS (inverted value) terminal of SRAM is
The SRAM chip select signal 111 output from the select signal generation circuit 110 is input.

CAS (inverted value) of the upper bank DRAM block 120 and the lower bank DRAM block 130
The DRAM column address latch timing signal 104 is connected to the terminal.

The chip select signal generation circuit 110 for generating the SRAM chip select signal 111 is
The configuration differs depending on the memory allocation of the system, etc.
In the present embodiment, the configuration thereof is not important and may be the same as that shown in the above-mentioned example of the prior art, and therefore detailed description thereof will be omitted.

RAS (inverted value) of upper bank DRAM block 120 and lower bank DRAM block 130
The DRAM row address latch timing signal input to the terminal is the RA of the microcomputer main body 100.
The DRAM row address latch timing signal 106 output from the S (inverted value) terminal is input as it is.

To the address input terminals A0 to A9 of the upper bank DRAM block 120 and the lower bank DRAM block 130, A1 to A10 of the address signal 105 output from the microcomputer main body 100 are input as they are, and similarly, the upper bank SRAM Block 14
0 and the address input terminals A0 to A14 of the lower bank SRAM block 150 respectively receive A1 to A15 of the output of the address signal 105 as they are.

As for the data bus, the upper 8 bits (D8 to D15) of the data bus signal 107 of the microcomputer main body 100 are set to the I / O 1 of the upper bank DRAM block 120 and the upper bank SRAM block 140.
To lower I / O 8 and lower 8 bits D0 to D7 of lower bank DRAM block 130 and lower bank SRAM.
Connect to I / O1 to I / O8 of block 150.

Next, the operation of the system according to the present embodiment at the time of Meiori access will be described. First, when accessing the memory with this system, D
It is necessary to specify the RAM allocation area. There are various methods as the method, but in this embodiment, the range of the DRAM allocation area and the address configuration of the DRAM are set in advance by software in the address map setting area 2
It shall be set to 03. When the microcomputer accesses the external memory, the address comparison circuit 204 determines whether or not the access target address value generated by the address modifier 208 is within the DRAM area set in the address map setting area 203. To be done.

An example of general DRAM access timing is shown in FIGS.

FIG. 3 shows an example of general DRAM access timing in the read cycle, and each signal is the signal used in FIGS. 1 and 2.

FIG. 4 shows an example of general DRAM access timing in a write cycle, and further includes an early write cycle and a late write cycle.
A write cycle is shown.

As shown in FIGS. 3 and 4, address input to the DRAM is divided into a row address and a column address.
The address output from 00 must be multiplexed in accordance with the structure of the DRAM to output the address signal.

7 and 8 show an example of CPU access timing (during DRAM access) of this embodiment.

In FIG. 7, an example of CPU access timing (DRAM in this embodiment at read timing)
Access time), and a clock (CLK) signal and the like are shown.

In FIG. 8, an example of the CPU access timing of this embodiment at the write timing (DRAM
(At the time of access) is shown.

A combination of address multiplexes according to the structure of the DRAM is shown in the output signal table from the address terminal at the time of accessing the DRAM of FIG.

FIG. 9 is a diagram showing a table of output signals from the address terminals when accessing the DRAM.

The combination of the multiplex of the row address and the column address is preset in the address map setting area 203 by software according to the address configuration of the DRAM. Address comparison circuit 20
If it is determined from the comparison result of 4 that the access target is the DRAM area, the address multiplexer 206
Thus, the address is multiplexed in the address configuration of the DRAM selected by the setting of the address map setting area 203 and output to the address bus 205.

Regarding the circuit for generating the address multiplex signal inside the address multiplexer 206,
Except for the function of selecting whether or not to multiplex according to the comparison result of the address comparison circuit 204, it is the same as the conventional multiplex signal generation circuit, and the method is not important in the present invention, so a detailed description thereof will be omitted.

Therefore, when accessing the DRAM by the microcomputer according to the present embodiment, a combination of address / multiplex signals corresponding to the DRAM configuration is sent from the microcomputer main body 100.
It is output at the timing shown in FIG.

When the SRAM is accessed by the microcomputer according to the present embodiment, the address comparison circuit 204 checks that the access target is not the DRAM, and the CPU access / access of the present embodiment shown in FIGS.
Each signal is output at the timing shown in the timing example (during normal access). Microcomputer body 100
All bits A0 to A23 are output at one time, and one memory cycle is completed in two states.

FIG. 5 shows each signal of the CPU access timing example of this embodiment at the read timing (during normal access), and FIG. 6 shows the CPU access timing of this embodiment at the write timing. Each signal of the example (during normal access) is shown.

As described above, according to this embodiment,
In a microcomputer having a plurality of address terminals for outputting an address to the outside, a dynamic RAM
It has a function of outputting a RAS (inverted value) timing signal and a CAS (inverted value) timing signal (hereinafter referred to as DRAM), and the microcomputer main body has means for discriminating whether the DRAM is accessed or not. Then, a microcomputer having a multiplex for controlling whether to output the address information for each access to the address terminal at one time or to output the address information to a certain specific address terminal by dividing the address information into two or more times is provided. can get. Further, particularly in a microcomputer having the above-mentioned function, a DRAM address configuration and a setting area of an assigned address range, a means for comparing the set address range with an access target address, and whether or not the address is multiplexed from the comparison result. It is also possible to obtain a microcomputer with a built-in address multiplexer having the function of switching between.

As described above, two kinds of CPU access timings are selected depending on the object to be accessed by the microcomputer, and when the DRAM is accessed, the address / multiplex signals of the combination corresponding to the DRAM configuration are output, which is easy. An SRAM and a DRAM as external memories can be connected to and accessed.

[0056]

As described above, according to the present invention,
By setting the address size and allocation area of the DRAM in the microcomputer in advance by software, SR from the same address output terminal
All bits of the address can be output at the same time at the time of AM or external I / O access, and the high-order address and the low-order address can be multiplexed and output at the time of DRAM access. In this case, the address output signal from the CPU body can be directly connected to the address input terminal of the memory, and the address latch circuit, row address /
Column address switching circuit and data bus
This eliminates the need for a buffer circuit, which makes it possible to easily design the circuit that connects the microcomputer and the memory, reduce the circuit scale, and reduce the board size. Also, two types of access timing are selected depending on the access target, making it efficient. The effect is that the memory can be accessed.

[Brief description of drawings]

FIG. 1 is a block diagram of a memory connection circuit of a microcomputer according to an embodiment of the present invention.

FIG. 2 is a block diagram of the inside of a CPU according to an embodiment of the present invention.

FIG. 3 is a timing chart showing a part of an access timing example of a general DRAM.

FIG. 4 is a timing diagram showing another part of FIG.

5 is a timing chart of a part of the CPU access timing example (during normal access) of FIG. 2;

FIG. 6 is a timing diagram of another part of FIG.

7 is an example of CPU access timing (DRA of FIG. 2)
It is a timing chart of a part of (M access time).

FIG. 8 is a timing diagram showing another part of FIG. 7.

FIG. 9 is a diagram showing an output signal table from an address terminal when accessing a DRAM.

FIG. 10 is a block diagram of a memory connection circuit example by a conventional microcomputer (example of V55).

FIG. 11 is a block diagram of the inside of the CPU of a conventional microcomputer (example of V55).

FIG. 12 is a block diagram of an example of a memory connection circuit by a conventional microcomputer (in the case of V35).

FIG. 13 is a block diagram of the inside of a CPU of a conventional (V35) microcomputer.

[Explanation of symbols]

100 Microcomputer main body 101,701 Data read strobe signal 102,702 High byte data write strobe signal 103,703 Low byte data write strobe signal 104 DRAM column address latch timing signal 105 Address signal 106,706 DRAM row address latch
Timing signal 107 Data bus signal 110, 710, 910 Chip select signal generation circuit 111, 711, 911 SRAM chip select signal 120, 720, 920 Upper bank DRAM block 130, 730, 930 Lower bank DRAM block 140, 740, 940 Upper bank SRAM block 150, 750, 950 Lower bank SRAM block 201, 801, 1001 Execution unit (EXU) 202, 802, 1002 Bus control unit (BCU) 203 Address map setting area 204 Address comparison circuit 205,805,1005 Address Bus 206,1006 Address Multiplexer 207,1007 Data Bus 208,808,1008 Address Module Buffer (ADM) 209, 809, 1009 Weight control circuit 210, 810, 1010 Status controller 700 V55 CPU main unit 704 Address strobe signal 705 Address signal 708 Address / data multiplex signal 712, 912 DRAM column address latch Timing signal 760 row address / column address switching circuit 761 row address / column address multiplex signal 770 address latch circuit 771 latch address signal 780 data bus buffer circuit 803 internal data bus 806 address / Data multiplexer 807 Address / data multiplex bus 900 V35 CPU body 901 Read cycle / write cycle Identification signal 902 A18 / Upper byte enable multiplex signal 903 lower memory bank selection signal 904 memory strobe signal (DRAM column
Address latch timing signal) 905 Address multiplex signal 906 Memory request signal (DRAM row address latch timing signal) 907 Data bus signal 909 DRAM refresh pulse signal 970 Upper address latch circuit

Claims (2)

[Claims] 1. A microcomputer having a microcomputer main body and a plurality of address terminals for outputting an address to an external device, wherein a row address timing signal and a CAS column address timing signal of a dynamic random access memory are provided. The microcomputer body has a function of outputting, and the microcomputer body has means for discriminating whether the memory is accessed or not, and outputs address information for each access to the address terminal at once. A microcomputer having a multiplex for controlling whether to output the address information divided into two or more times to a specific address terminal. 2. In a microcomputer having the above function, an address configuration of a DRAM and a setting area of an assigned address range, a means for comparing a set address range and an access target address, and an address are multiplexed from the comparison result. A microcomputer characterized by incorporating an address multiplexer having a function of switching whether or not it is used.