JP3190847B2 - Data transfer control device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a data transfer control device, and more particularly to a data transfer control device for processing data transfer between two types of memories having different access units.

[0002]

2. Description of the Related Art In an information processing system, data transfer between memories is usually performed on various occasions. For example, in the example of FIG. 7, in order to perform data transfer between the extended storage device 74 connected to the data transfer control device 72 and the main storage device 71, data in the main storage device 71 is transferred via the data bus 73. The control device 72 reads the data, temporarily stores it in the internal buffer 720, and writes it in the extended storage device 74, or conversely transfers the data from the extended storage device 74 written in the buffer 720 to the main storage device 71. Is done.

Generally, in order to enable high-speed memory transfer, the main storage device 71 has a plurality of bytes, for example, 4 bytes or 8 bytes.
One access unit (called a word or the like) is constituted by bytes, and the data bus width of the data bus 73 is equal to one unit access width. Data can be accessed from the central processing unit 70 in access units. is there. Therefore, in a normal transfer in which all bytes of one access unit of the data supply side (read side) memory are written in one access unit of the data storage side (write side) memory, 1 byte for each memory is used. A normal transfer method using a move instruction or the like by multiple accesses is sufficient. However, transferring data from a byte position in the middle of the access unit of the supply memory to an area from a byte position in the middle of the access unit of the storage memory cannot be realized by a normal method.

For example, FIG. 5A shows that the access unit is 8
An example of reading data from an intermediate byte position instead of an 8-byte boundary and a 256-byte boundary and writing data to an intermediate byte position between memories starting from a byte boundary and a 256-byte boundary and accessible in units of 4 bytes. Is shown. As a method for realizing such transfer, there is the following method.

[0005] That is, the access unit of the memory on the supply side and the storage side is converted into 4 bytes, and the instruction of the central processing unit 70 causes the data transfer control unit 72 to use the partial write function which makes only a specific byte effective. To read and write data. When the data transfer shown in FIG. 5A is performed, data is read from the memory on the supply side, and the data in the access unit of the memory on the supply side including the storage area is stored in the read buffer from the memory on the storage side. Here, assuming that the access unit of the buffer storing the data is the same as the access unit of the data transfer, the data of the access unit of the supply side memory is written at the position corresponding to the storage start address of the storage side memory, and Generate data according to the memory access unit. The partially rewritten data is returned to the extended storage device again.

[0006]

In the conventional data transfer control device as described above, the transfer speed is extremely slow because of the 4-byte transfer, and the access to the supply side and storage side memory is frequently performed. The time for occupying the data bus 73 becomes longer. Therefore, there is a disadvantage that the performance of the other processing units sharing the data bus 73 is greatly affected.

In addition, two accesses are required for one access unit of the storage side memory, so that one memory transfer requires two memory transfers, and the transfer speed is low and other processing units are not used. There are many adverse effects on

An object of the present invention is to provide a data transfer control device capable of transferring data of an arbitrary length from an arbitrary byte position of a supply side memory to an area from an arbitrary byte position of a storage side memory at a high speed. It is in.

[0009]

A data transfer control device according to the present invention is a data transfer control device for performing data transfer between two types of memories having different access units, wherein an arbitrary address of a data supply side memory is started. Data having an arbitrary data length is sequentially read out as an address, and the data having the arbitrary data length is sequentially written using an arbitrary address in a data storage side memory as a start address.

In the data transfer control device according to the present invention, the transfer start position of the supply side memory and the storage start position of the storage side memory are shifted to a position of an arbitrary minimum transfer byte unit in an access unit of each memory. It is configured to be.

Further, the data transfer control device of the present invention comprises a plurality of buffers for storing read data for a unit access of a data supply side memory, and an address register for controlling reading of data from the buffers for each buffer. A shift control register for setting a shift amount for shifting data stored in the buffer to a storage start position of a data storage side memory; and a shift for shifting data stored in the buffer according to an instruction of the shift control register. A circuit, a flag indicating whether or not to control the next buffer with the same control information as the control information of the current buffer when reading data continuously from the buffer; The buffer according to the transfer start address of the supply side memory and the storage start address of the storage side memory. Setting the write address, the shift amount, and the flag, sequentially writing data from the supply side memory to the buffer, shifting the data read out from the buffer according to the shift amount, and accessing the storage side memory. And a control circuit for sequentially transmitting the data in units and invalidating the control information of the next buffer by the flag.

Further, in the data transfer control device of the present invention, the control circuit includes a data read control unit for instructing reading of data from the supply memory, a first register for setting a start address of the supply memory, A data write control unit for instructing writing of data to the storage side memory, a second register for setting a start address of the storage side memory, and the shift according to the contents of the first register and the contents of the second register. A subtraction circuit for determining the amount;
A third register for setting the number of bytes of data to be transferred, a buffer read address control unit for setting a read start address of the buffer according to the contents of the first register, and a buffer being transferred according to the contents of the third register. It comprises a final block determining unit for determining whether or not the data is the last block, and a flag generating unit for generating a flag for setting control information of a succeeding buffer.

That is, the data transfer control device according to the present invention supplies data by the hardware operation based on n buffers for storing data in the supply side memory and n buffer control information provided for each buffer. Regardless of the transfer start position of the side memory and the storage start position of the storage side memory at any position in the minimum transfer byte unit, the read data of the supply side memory is read from a desired address position based on the buffer control information. The difference between the transfer start position and the storage start position is absorbed by writing to the buffer and shifting and reading the data according to the shift amount determined from the buffer control information. Further, when a difference occurs between the number of write buffers and the number of read buffers due to the shift operation at the time of reading of the buffer, control of the subsequent buffer is performed by a subsequent buffer control invalidation instruction in the read control information provided for each buffer. The operation is stopped, and unnecessary buffer operations are deleted by performing read control of the succeeding buffer based on the preceding buffer read control information. Therefore, data of an arbitrary minimum transfer unit length from the transfer start position of the minimum transfer unit of the supply memory can be stored in the area from the storage start position of the minimum transfer unit of the storage memory without unnecessary access to the storage memory. Can be transferred to

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. 1, a data transfer control device 10 according to the present invention includes a buffer 1, a register 2, a register 3,
It comprises an address register 4, a shift control register 5, a shift circuit 6, a flag 7, and a control circuit 8, and is incorporated in, for example, the control unit 721 in FIG.
Necessary information is set from the main control unit constituted by one other part, and the operation is started by being activated. Here, the access unit of the supply side memory is 256 bytes, the access unit of the storage side memory is 8 bytes, and the minimum transfer unit between the memories is 4 bytes.

The buffer 1 is composed of 32 bytes.times.256 words and stores data read from the memory on the supply side. Then, control is performed with a 256-byte capacity as one unit. The buffer 1 contains 256 bytes from the 256-byte boundary including the storage memory start address given by the main control unit.
Byte continuous data is stored.

The register 2 is a write data register of the buffer 1.

The address register 4 is a read address register for the buffer 1. The upper 3 bits are buffer numbers of a plurality of buffers configured as 32 bytes × 8 words as one unit, and the lower 3 bits are a reading start address of the buffer configured as 1 unit. The read start address of the lower 3 bits of the address register 4 generates a continuous address for the number of words specified by the register.

The shift circuit 6 shifts the data stored in the buffer 1 in units of 256 bytes by a shift amount corresponding to the value set in the shift control register 5 in units of 4 bytes and reads the data. FIG. 2 shows how the shift circuit 6 shifts and reads data from the buffer in accordance with the value set in the shift control register 5.

The register 3 is a 32-byte register for temporarily storing the output of the shift circuit 6 and writing the output to the storage memory. Then, data is sequentially transferred to the storage side memory in units of 8 bytes, which is an access unit of the storage side memory.

The lower three bits of the address register 4 include
Information uniquely determined from the supply start address of the supply side memory and the storage start address of the storage side memory is held. That is, the lower 3 bits of the address register 4 are 3 bits within the 256 byte boundary of the supply start address of the supply memory.
A two-byte boundary address is specified. FIG. 3 shows what values are set in the shift control register 5 according to the supply start address of the supply side memory and the storage start address of the storage side memory. In other words, the data in the buffer shown in FIG. 3A is transmitted from the shift circuit according to the shift amount as shown in FIG. 3B.

The flag 7 indicates control information generated in a series of buffer units when a difference occurs between the number of write buffers and the number of read buffers due to a shift operation at the time of reading of a buffer having 32 bytes × 8 words as one unit. Indicates that the control of the subsequent buffer is stopped. At that time, the reading control of the succeeding buffer is performed by the buffer reading control information preceding the flag.

The control circuit 8 starts the control of the data transfer control device 10 when the data length to be transferred, the supply start address, and the storage start address are set and activated by the host control unit.

FIG. 4 is a block diagram showing details of the control circuit 8 described above. In the figure, a control circuit 8 includes a data read control unit 41 for performing data read control on a supply side memory, a data write control unit 42 for performing data write control on a storage side memory, a register 43 in which a storage side address is set, The register 44 in which the side address is set, the flag generator 45 for determining the value of the flag 7 for invalidating the control of the succeeding buffer, the subtraction circuit 46 for determining the value of the shift control register 5, and the number of transfer bytes are set. In accordance with the register 47 and the number of bytes held in the register 47, the buffer read word number of one unit is determined, and the buffer read word is read from the buffer read start word of one unit determined from the read word number and the supply start address of the supply side memory. One unit of buffer read address control unit 48 for determining address, register 4 Number of bytes stored contains a final block determining unit 49, the buffer management unit 50 for managing a buffer which is divided into a unit for detecting whether 256 bytes or less in the.

First, prior to the transfer between the memories, the upper control unit sets the number of bytes to be transferred to the register 47, the start address of the supply-side memory to the register 3, and the start address of the storage-side memory to the register 44. The control circuit 8 is activated.

The subtraction circuit 46 is a 5-bit subtraction circuit. As can be seen from FIG. 2, the lower 5 bits which are addresses within the 32-byte boundary of the supply start address and the lower 3 bits which are the addresses within the 8-byte boundary of the storage start address. The shift amount at the time of buffer reading is determined by subtracting the bit, and the value to be set is output to the shift control register 5.

The flag generation unit 45 calculates the value of the register 47 in which the number of transfer bytes is set, and the supply start address indicating the buffer read start word of one unit.
The flag value is determined from the 3-bit value from the lower 6th bit, which is a 2-byte boundary address, and the buffer read shift amount generated by the subtraction circuit 46. That is, if the last block is determined by the last block determining unit 49 to be the last block, the register 4 storing the number of transfer bytes is used.
The value to be set to the flag 7 is output if the value obtained by adding the value of 7 and the 32-byte boundary address within the 256-byte boundary of the supply start address and subtracting the shift amount is 256 bytes.

The buffer read address control unit 48 generates a read address for executing reading of eight words in order from one unit of buffer reading start word. When the last block is detected by the last block determination unit 49, the number of words read out of the last block is calculated from the number of remaining transfer bytes held in the register 47, and the read address of the last block is generated. The value to be set in the lower 3 bits of 4 is output.

The buffer management unit 50 obtains the number of buffers in the data transfer from the supply start address set in the register 44, the storage start address set in the register 43, and the transfer size set in the register 47. , And a value to be set in the upper 3 bits of the address register 4 is output.

Next, the operation of the data transfer control device 10 will be described.

FIG. 5 shows that when the value of the flag 7 is 0, that is, in the method of using a buffer determined in one unit, there is a difference between the number of write buffers from the supply side memory and the number of read buffers for transferring data to the storage side memory. Here is an example of a case in which this does not occur.
FIG. 6 shows an example in which the value of the flag 7 is 1, that is, a difference occurs between the number of write buffers from the supply side memory and the number of read buffers for transferring data to the storage side memory, and the next buffer control is invalidated. Is shown.

In FIG. 5, the transfer byte number is 320 bytes (0 × 140), and in FIG. 6, the transfer byte number is 256 bytes (0 × 100). In any case, supply start address S
The SA is 284 bytes (0x15C), and the storage start address SDA is 256 bytes (0x100). further,
FIGS. 5A and 6A show access units of the supply-side memory and the storage-side memory, and A0 to L6 described in each access unit are 4-byte data.

FIG. 5A shows a transfer size of 320 bytes from 8-byte data d1 of the supply start address 284 bytes of the access unit WS1 of the supply side memory and a transfer size of 320 bytes from the storage start address 256 bytes of the storage side memory. This shows a case where data is transferred to a byte area.

When the control circuit 8 is started by the upper control unit, data transfer of a designated transfer size is started according to the set supply start address and storage start address.
First, the data read control unit 41 holds the read data of the supply side memory according to the supply start address set by the host control unit and the buffer number specified by the buffer management unit 50.

Here, the access unit of the supply side memory is 2
Since it is 56 bytes, the supply start address set in the register 44 is set in the register 47 from the 256 byte boundary address (in this case, the address is 256 bytes) to the supply start address set in the register 44 (284 bytes in this case). Of the supply-side memory (in this case, the added transfer size (in this case, 320 bytes))
The data including (284 bytes + 320 bytes) is read from the supply side memory in units of 256 bytes. That is, words corresponding to WS1 and WS2 shown in FIG. 5A are sequentially read, and the buffer number n shown in FIG.
And n + 1.

The buffer to be used is reserved by the buffer management unit 50 in advance, and is designated by two consecutive buffer numbers determined from the supply start address and the transfer size.
Here, the writing of the buffer is performed in units of 256 bytes, and the reading of the buffer is similarly controlled in units of 256 bytes. For WS1 and WS2 read from the supply-side memory as described above, data to be written to the storage-side memory is represented by BWS1 and BWS2, the control unit for reading the buffer is also 2, and the value of the flag 7 is 0. .

Next, the data writing control unit 42 generates buffer control information for performing buffer reading for writing to the storage side memory. First, the buffer read address control unit 48 obtains the lower three bits BSA of the buffer read start address where valid transfer data is held, from the supply start address set in the register 44.

The upper three bits of the buffer read start address indicate the buffer number BNO divided into one unit obtained when data is read from the supply side memory, and the value output as the write buffer number by the buffer management unit 50 Is held. That is, as shown in FIG. 5B, the value set in the address register 4 is BNO + BSA. The timing at which this buffer number is set is equivalent to the timing at which a value is set in the shift control register 5.

Since one word of this buffer is composed of 32 bytes, BSA is set to the supply side start address of 25 bytes.
This is a value obtained by dividing the address within the 6-byte boundary by the number of bytes of one word 32. In this case, BNO is arbitrary, and BSA is 0111100 in the lower byte of the supply start address SSA preset in the register 43 from the upper control unit. 0 is output. Here, the BSA indicates a pointer in units of 32 bytes for 256 bytes in a unit of reading one buffer.

Next, the shift amount BSP at the time of buffer reading is determined from the difference between the supply start address and the storage start address. The BSP indicates a buffer read pointer per word to the BSA, and is given by an address within a 32-byte boundary of the supply side address of the register 44. If the minimum unit of the data transfer unit is 4 bytes, the 4-byte unit is used. It is obtained as a shift amount. Since the access unit of the storage-side memory is 8 bytes, if the storage-side start address is given on a 4-byte boundary, the difference is absorbed by the subtraction circuit 46. In this case, the lower 5 bits of the supply-side start address SSA are 7 which is a value obtained by dividing 11100 (address within the 32-byte boundary of the supply start address) by 4, and the lower 3 bits of the storage-side start address DSA are 000 (the 8 byte boundary of the storage-side address). (Internal address) divided by 4 is 0, and the shift amount BSP in 4-byte units is 7 from FIG.

The obtained buffer read start address B
The SA and the shift amount BSP in units of 4 bytes are set in the address register 4 and the shift control register 5, respectively.
It is used as control data of 256 bytes which is one unit of buffer size.

As shown in FIG. 5B, the buffer reading process is started from the BSA and BSP, and the first 32 bytes are shifted by the shift circuit 6 according to the value set in the shift control register 5 and stored in the register 3. Is done. At this time, the 32-byte data stored in the register 3 is read across one word of the buffer.
The address of the word is generated, and continuous 32-byte data spanning two words is read from the buffer. However, when the shift amount is 0, the address is not incremented because reading is possible without straddling two words.

Thereafter, reading is performed eight times, reading of one unit of buffer (256 bytes) is completed, a buffer release instruction is issued to the buffer management unit 50, and control is passed to the next buffer reading control. Here, the value of the flag 7 is 0
If the last block is determined by the last block determination unit 49, the number of words to be read out from the buffer is calculated from the remaining transfer size set in the register 47. Perform the release.

FIG. 6 (a) shows the transfer size of 256 bytes from the 8-byte data d1 of the supply start address 284 bytes of the access unit WS1 of the supply side memory and the transfer size of 256 bytes from the storage start address 256 bytes of the storage side memory. This shows a case where data is transferred to a byte area.

When the control circuit 8 is started by the upper control unit, data transfer of a designated transfer size is started according to the set supply start address and storage start address.
First, data of a specified transfer size is read from the supply start address in the same manner as in FIG. 5, and WS1 and WS2 in FIG.
Are sequentially read and held in two buffers of buffer numbers n and n + 1. Here, the reading of the buffer is also controlled in units of 256 bytes. For WS1 and WS2 read from the supply side memory, data to be written to the storage side memory is represented by BWS1, and the control unit for reading out the buffer is 1 unit. If it is found, the reading from the buffer is completed. Therefore, a difference occurs between the number of write buffers and the number of read buffers, and the value of the flag 7 becomes 1.

Next, the data writing control unit 42 generates buffer control information for performing buffer reading for writing to the storage side memory in exactly the same manner as in FIG. Eight readings are performed based on the buffer control information obtained as described above, and one unit of buffer (256
Byte) is completed. And the buffer management unit 5
0 is instructed to release the buffer, and the final block determination unit 4
Until the block 9 is determined to be the last block, the process proceeds to the read control of the next buffer.

Here, since the value of the flag 7 is 1, FIG.
As shown in (b), reading of the transfer data is completed without waiting for reading of the last buffer number at the time of writing. Therefore, the reading of the last buffer is invalidated by the flag 7, and the buffer is released.

Although the embodiments of the present invention have been specifically described above, the present invention is not limited to these embodiments. For example, the configuration of a buffer provided in one unit provided in the data transfer control device 10 can be changed according to the access unit of the supply side memory and the storage side memory. Further, it is also possible to adopt a configuration in which the upper control unit has the management of the supply address, the storage address, and the number of transfer bytes added to the control circuit 8, and the data read and write functions.

[0049]

As described in detail above, the data transfer control device according to the present invention absorbs the difference between the access units of the supply memory and the storage memory by controlling the writing and reading of the buffer. Therefore, data of an arbitrary length from an arbitrary byte position in the supply side memory can be transferred at high speed to an area from an arbitrary byte position in the storage side memory. Therefore, there is an effect that the influence on other processing devices sharing the memory can be minimized.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is an explanatory diagram showing a shift amount when storing transfer data.

FIG. 3 is an explanatory diagram showing a relationship between a buffer and a shift amount.

FIG. 4 is a block diagram showing details of a control circuit.

FIG. 5 is an explanatory diagram showing an operation example of the present invention.

FIG. 6 is an explanatory diagram showing another operation example of the present invention.

FIG. 7 is a block diagram showing an example of data transfer between memories.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 buffer 2, 3 register 4 address register 5 shift control register 6 shift circuit 7 flag 8 control circuit 10 data transfer control device 41 data read control unit 42 data write control unit 43, 44, 47 register 45 flag generation unit 46 subtraction circuit 48 Buffer read address control unit 49 Last block determination unit 50 Buffer management unit

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G06F 12 / 04,12 / 06,13 / 36

Claims (2)

(57) [Claims] 1. A data transfer control device for performing data transfer between two types of memories having different access units, comprising: a plurality of buffers for storing read data for a unit access of a data supply side memory; An address register for controlling reading of data for each buffer, a shift control register for setting a shift amount for shifting data stored in the buffer to a storage start position of a data storage side memory, and an instruction of the shift control register. A shift circuit that shifts data stored in the buffer according to: and a flag that indicates whether to control the next buffer with the same control information as the control information of the current buffer when continuously reading data from the buffer, The data length of the transfer data specified by the host device, the transfer start address of the supply side memory, The write address of the buffer, the shift amount, and the flag are set in accordance with the storage start address of the storage side memory, and the data supplied from the supply side memory are sequentially read from the adjacent data.
A control circuit for writing data into the buffer different from the buffer, shifting data read from the buffer according to the shift amount, sequentially sending the data to the storage side memory in access units, and invalidating control information of the next buffer by the flag. A data transfer control device comprising: 2. The data transfer control device according to claim 1 , wherein the control circuit is a data read control unit that instructs reading of data from a supply memory, and a first register that sets a start address of the supply memory. A data write control unit that instructs writing of data to the storage memory; a second register that sets a start address of the storage memory; and a content of the first register and a content of the second register. A subtraction circuit for determining the shift amount; a third register for setting the number of bytes of data to be transferred; a buffer read address control unit for setting a buffer read start address according to the contents of the first register; A last block determining unit that determines whether the data being transferred is the last block according to the contents of the third register; And a flag generation unit for generating a flag for setting control information of a buffer to be transferred.