JPS6324747U - - Google Patents
Info
- Publication number
- JPS6324747U JPS6324747U JP11676986U JP11676986U JPS6324747U JP S6324747 U JPS6324747 U JP S6324747U JP 11676986 U JP11676986 U JP 11676986U JP 11676986 U JP11676986 U JP 11676986U JP S6324747 U JPS6324747 U JP S6324747U
- Authority
- JP
- Japan
- Prior art keywords
- fdd
- units
- selection signal
- predetermined number
- unit selection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000010586 diagram Methods 0.000 description 1
Description
第１図は本考案の実施例を示すＦＤＤコントロ
ール回路のブロツク図、第２図は第１図のメモリ
ＲＡＭの記憶データ例である。
ＦＤＣ……ＦＤＤ制御素子、ＲＡＭ……ランダ
ムアクセスメモリ（ユニツト選択信号記憶部）。
FIG. 1 is a block diagram of an FDD control circuit showing an embodiment of the present invention, and FIG. 2 is an example of data stored in the memory RAM shown in FIG. FDC...FDD control element, RAM...Random access memory (unit selection signal storage section).
Claims (1)
ク可能にしたＦＤＤ制御素子を備えコンピユータ
制御によりＦＤＤユニツトを制御するＦＤＤコン
トロール回路において、 各ユニツト選択に先立つてコンピユータ制御に
より、前記所定のユニツト数を越えたユニツトの
うちから前記所定のユニツト数を限度として各ユ
ニツトが適宜指定されて該各指定毎に当該各ユニ
ツト選択信号が書込まれまたは書替えられて、該
書込みまたは書替えられたユニツト選択信号が前
記ＦＤＤ制御素子の選択信号によつて読出される
ユニツト選択信号記憶部を設けていることを特徴
とする ＦＤＤコントロール回路。[Claims for Utility Model Registration] In an FDD control circuit that is equipped with an FDD control element that can simultaneously seek a predetermined number of FDD units and controls the FDD units under computer control, the Out of the units exceeding the predetermined number of units, each unit is appropriately designated up to the predetermined number of units, and each unit selection signal is written or rewritten for each designation, and the writing or rewriting is performed. An FDD control circuit comprising: a unit selection signal storage section in which a unit selection signal is read out in accordance with a selection signal of the FDD control element.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11676986U JPH0739086Y2 (en) | 1986-07-31 | 1986-07-31 | FDD control circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11676986U JPH0739086Y2 (en) | 1986-07-31 | 1986-07-31 | FDD control circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6324747U true JPS6324747U (en) | 1988-02-18 |
| JPH0739086Y2 JPH0739086Y2 (en) | 1995-09-06 |
Family
ID=31001668
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11676986U Expired - Lifetime JPH0739086Y2 (en) | 1986-07-31 | 1986-07-31 | FDD control circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0739086Y2 (en) |
-
1986
- 1986-07-31 JP JP11676986U patent/JPH0739086Y2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0739086Y2 (en) | 1995-09-06 |