JPH0230199U - - Google Patents

Info

Publication number
JPH0230199U
JPH0230199U JP10594688U JP10594688U JPH0230199U JP H0230199 U JPH0230199 U JP H0230199U JP 10594688 U JP10594688 U JP 10594688U JP 10594688 U JP10594688 U JP 10594688U JP H0230199 U JPH0230199 U JP H0230199U
Authority
JP
Japan
Prior art keywords
memory
block
blocks
designating
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10594688U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP10594688U priority Critical patent/JPH0230199U/ja
Publication of JPH0230199U publication Critical patent/JPH0230199U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Static Random-Access Memory (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案のメモリ制御装置の概要を表わ
したブロツク図、第2図および第3図は本考案の
一実施例を説明するためのもので、そのうち第2
図はDRAMの大容量メモリを用いたメモリ制御
装置の構成を表わした回路図、第3図はデータ書
き込み時の各信号のタイミングを表わしたタイミ
ング図である。 1……大容量メモリ、3……アドレスチツプイ
ネーブル回路、7……タイミングコントローラ。
FIG. 1 is a block diagram showing an outline of the memory control device of the present invention, and FIGS. 2 and 3 are for explaining one embodiment of the present invention.
The figure is a circuit diagram showing the configuration of a memory control device using a large-capacity DRAM memory, and FIG. 3 is a timing diagram showing the timing of each signal during data writing. 1...Large capacity memory, 3...Address chip enable circuit, 7...Timing controller.

Claims (1)

【実用新案登録請求の範囲】 複数のブロツクに区分けされたメモリと、 このメモリ内の前記ブロツクを同時に複数指定
するブロツク指定手段と、 このブロツク指定手段によつて指定されたブロ
ツク内のデータを消去するデータ消去手段 とを具備することを特徴とするメモリ制御装置。
[Claims for Utility Model Registration] A memory divided into a plurality of blocks, a block designating means for simultaneously designating a plurality of blocks in the memory, and erasing data in the block designated by the block designating means. 1. A memory control device comprising: data erasing means.
JP10594688U 1988-08-12 1988-08-12 Pending JPH0230199U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10594688U JPH0230199U (en) 1988-08-12 1988-08-12

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10594688U JPH0230199U (en) 1988-08-12 1988-08-12

Publications (1)

Publication Number Publication Date
JPH0230199U true JPH0230199U (en) 1990-02-26

Family

ID=31339017

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10594688U Pending JPH0230199U (en) 1988-08-12 1988-08-12

Country Status (1)

Country Link
JP (1) JPH0230199U (en)

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