JPS63126935U - - Google Patents

Info

Publication number
JPS63126935U
JPS63126935U JP1873487U JP1873487U JPS63126935U JP S63126935 U JPS63126935 U JP S63126935U JP 1873487 U JP1873487 U JP 1873487U JP 1873487 U JP1873487 U JP 1873487U JP S63126935 U JPS63126935 U JP S63126935U
Authority
JP
Japan
Prior art keywords
buffer memory
microcomputer
external storage
storage device
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1873487U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1873487U priority Critical patent/JPS63126935U/ja
Publication of JPS63126935U publication Critical patent/JPS63126935U/ja
Pending legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の一実施例のブロツク図、第2
図はマイコンの処理フロー図、第3図は演算部の
処理フロー図である。 1…マイコン、2…外部記憶装置、3…書き込
み用バンクアドレス指定レジスタ、4…バツフア
メモリ、5…読み出し用バンクアドレス指定レジ
スタ、6…演算部、7…バンクステータスレジス
タ、8…計数回路、9…起動指令。
Figure 1 is a block diagram of one embodiment of the present invention;
The figure is a process flow diagram of the microcomputer, and FIG. 3 is a process flow diagram of the arithmetic unit. DESCRIPTION OF SYMBOLS 1... Microcomputer, 2... External storage device, 3... Bank address specification register for writing, 4... Buffer memory, 5... Bank address specification register for reading, 6... Arithmetic unit, 7... Bank status register, 8... Counting circuit, 9... Start command.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 外部記憶装置と、外部記憶装置のデータを格納
するバツフアメモリと、バツフアメモリのデータ
を読み出して演算する演算部と、上記の3者を制
御するマイコン(マイクロコンピユータ)より成
るマイコン応用機器において、バツフアメモリへ
のデータ格納と読み出しを非同期かつ連続して行
なうことを特徴とする循環式バツフアメモリ制御
方式。
In a microcomputer-applied device consisting of an external storage device, a buffer memory that stores data in the external storage device, an arithmetic unit that reads data from the buffer memory and performs calculations, and a microcomputer that controls the above three, A cyclic buffer memory control method characterized by storing and reading data asynchronously and continuously.
JP1873487U 1987-02-13 1987-02-13 Pending JPS63126935U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1873487U JPS63126935U (en) 1987-02-13 1987-02-13

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1873487U JPS63126935U (en) 1987-02-13 1987-02-13

Publications (1)

Publication Number Publication Date
JPS63126935U true JPS63126935U (en) 1988-08-19

Family

ID=30812678

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1873487U Pending JPS63126935U (en) 1987-02-13 1987-02-13

Country Status (1)

Country Link
JP (1) JPS63126935U (en)

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